View MPD789426GK-9ET_1298316.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

users manual m m m m pd789425 m m m m pd789445 m m m m pd789426 m m m m pd789446 m m m m pd789435 m m m m pd789455 m m m m pd789436 m m m m pd789456 m m m m pd78f9436 m m m m pd78f9456 m m m m pd789426, 789436, 789446 789456 subseries 8-bit single-chip microcontrollers printed in japan document no. u15075ej1v0um00 (1st edition) date published november 2000 n cp(k) ? 1999 2000
2 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 3 eeprom is a trademark of nec corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. osf/motif is a trademark of open software foundation, inc. news and news-os are trademarks of sony corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 users manual u15075ej1v0um00 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: m pd78f9436, 78f9456 the customer must judge the need for license: m pd789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 m8e 00.4 the information in this document is current as of september, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).
users manual u15075ej1v0um00 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
6 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 7 introduction target readers this manual is intended to give user engineers an understanding of the functions of the m pd789426, 789436, 789446, and 789456 subseries to design and develop its application systems and programs. target products: m pd789426 subseries: m pd789425, 789426 m pd789436 subseries: m pd789435, 789436 m pd789446 subseries: m pd789445, 789446 m pd789456 subseries: m pd789455, 789456 purpose this manual is designed to deepen your understanding of the following functions using the following organization. organization two manuals are available for the m pd789426, 789436, 789446, and 789456 subseries: this manual and the instruction manual (common to the 78k/0s series). m pd789426, 789436, 789446, and 789456 subseries users manual 78k/0s series users manual instructions pin functions internal block functions interrupts other internal peripheral functions cpu function instruction set instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. to understand the overall functions of the m pd789426, 789436, 789446, and 789456 subseries ? read this manual in the order of the contents . how to read register formats ? the name of a bit whose number is enclosed in brackets is reserved for the assembler and is defined for the c compiler by the header file sfrbit.h. to learn the detailed functions of a register whose register name is known ? see appendix c register index . to learn the details of the instruction functions of the 78k/0s series ? refer to 78k/0s series instructions users manual (u11047e) separately available.
8 users manual u15075ej1v0um00 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document no. document name japanese english m pd789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 preliminary product information u14493j u14493e m pd78f9436, 78f9456 preliminary product information to be prepared to be prepared m pd789426, 789436, 789446, 789456 subseries users manual u 15075j this m anual 78k/0s series instructions users manual u 11047j u 11047e 78k/0, 78k/0s series flash memory write application note u14458j u14458e documents related to development tools (users manuals) document no. document name japanese english operation u11622j u11622e assembly language u11599j u11599e ra78k0s assembler package structured assembly language u11623j u11623e operation u11816j u11816e cc78k/0s c compiler language u11817j u11817e sm78k0s, sm78k0 system simulator ver. 2.10 or later windows tm based operation u14611j to be prepared sm78k series system simulator external part user open interface specifications u10092j u10092e id78k0s-ns integrated debugger windows based reference u12901j u12901e id78k0-ns, id78k0s-ns integrated debugger ver. 2.20 or later windows based operation u14910j to be prepared ie-78k0s-ns u13549j u13549e ie-789456-ns-em1 to be prepared to be prepared caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
users manual u15075ej1v0um00 9 document related to embedded software (users manual) document no. document name japanese english 78k/0s series os mx78k0s fundamental u12938j u12938e other related documents document no. document name japanese english semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to microcomputer-related products by third parties u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
10 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 11 contents chapter 1 general ........................................................................................................... ................25 1.1 features.................................................................................................................... ...................25 1.2 applications ................................................................................................................ ................25 1.3 ordering information ........................................................................................................ .........26 1.4 pin configuration (top view) ................................................................................................ ....27 1.4.1 pin configuration of m pd789426, 789436 subseries (top view) ................................................. 27 1.4.2 pin configuration of m pd789446, 789456 subseries (top view) ................................................. 28 1.5 78k/0s series lineup ........................................................................................................ .........30 1.6 block diagram ............................................................................................................... .............32 1.6.1 block diagram of m pd789426, 789436 subseries........................................................................ 32 1.6.2 block diagram of m pd789446, 789456 subseries........................................................................ 33 1.7 overview of functions....................................................................................................... ........34 chapter 2 pin functions.................................................................................................... ............37 2.1 list of pin functions....................................................................................................... ...........37 2.2 description of pin functions ................................................................................................ ....40 2.2.1 p00 to p03 (port 0)....................................................................................................... ................ 40 2.2.2 p10, p11 (port 1)......................................................................................................... ................. 40 2.2.3 p20 to p26 (port 2)....................................................................................................... ................ 40 2.2.4 p30 to p33 (port 3)....................................................................................................... ................ 41 2.2.5 p50 to p53 (port 5)....................................................................................................... ................ 41 2.2.6 p60 to p65 (port 6)....................................................................................................... ................ 41 2.2.7 p70 to p72 (port 7)....................................................................................................... ................ 42 2.2.8 p80, p81 (port 8)......................................................................................................... ................. 42 2.2.9 p90 to p97 (port 9)....................................................................................................... ................ 42 2.2.10 s0 to s14................................................................................................................ ...................... 42 2.2.11 com0 to com3 ............................................................................................................. ............... 42 2.2.12 v lc0 to v lc2 ............................................................................................................................... .... 42 2.2.13 caph, capl ............................................................................................................... ................. 42 2.2.14 reset.................................................................................................................... ...................... 42 2.2.15 x1, x2................................................................................................................... ........................ 42 2.2.16 xt1, xt2 ................................................................................................................. ..................... 42 2.2.17 v dd ............................................................................................................................... ................. 43 2.2.18 v ss ............................................................................................................................... ................. 43 2.2.19 v pp ( m pd78f9436, 78f9456 only)................................................................................................ 43 2.2.20 ic (mask rom version only)............................................................................................... .......... 43 2.3 pin input/output circuits and recommended connection of unused pins ........................44 chapter 3 cpu architecture................................................................................................. ......47 3.1 memory space ................................................................................................................ ............47 3.1.1 internal program memory space............................................................................................. ...... 53
12 users manual u15075ej1v0um00 3.1.2 internal data memory (internal high-speed ram) space .............................................................. 54 3.1.3 special function register (sfr) area...................................................................................... ....... 54 3.1.4 data memory addressing.................................................................................................... .......... 55 3.2 processor registers......................................................................................................... ......... 61 3.2.1 control registers ......................................................................................................... .................. 61 3.2.2 general-purpose registers ................................................................................................. ........... 64 3.2.3 special function registers (sfrs) ......................................................................................... ........ 65 3.3 instruction address addressing.............................................................................................. 68 3.3.1 relative addressing ....................................................................................................... ............... 68 3.3.2 immediate addressing ...................................................................................................... ............ 69 3.3.3 table indirect addressing ................................................................................................. ............ 70 3.3.4 register addressing....................................................................................................... ............... 70 3.4 operand address addressing.................................................................................................. 71 3.4.1 direct addressing......................................................................................................... ................. 71 3.4.2 short direct addressing................................................................................................... .............. 72 3.4.3 special function register (sfr) addressing ................................................................................ .. 73 3.4.4 register addressing....................................................................................................... ............... 74 3.4.5 register indirect addressing .............................................................................................. ........... 75 3.4.6 based addressing .......................................................................................................... ............... 76 3.4.7 stack addressing .......................................................................................................... ................ 76 chapter 4 port functions................................................................................................... ........ 77 4.1 port functions .............................................................................................................. ............. 77 4.2 port configuration.......................................................................................................... ........... 80 4.2.1 port 0 .................................................................................................................... ........................ 81 4.2.2 port 1 .................................................................................................................... ........................ 82 4.2.3 port 2 .................................................................................................................... ........................ 83 4.2.4 port 3 .................................................................................................................... ........................ 89 4.2.5 port 5 .................................................................................................................... ........................ 91 4.2.6 port 6 .................................................................................................................... ........................ 92 4.2.7 port 7 .................................................................................................................... ........................ 93 4.2.8 port 8 ( m pd789426, 789436 subseries only) ............................................................................... 94 4.2.9 port 9 ( m pd789426, 789436 subseries only) ............................................................................... 95 4.3 registers controlling port function........................................................................................ 9 6 4.4 port function operation ..................................................................................................... .... 102 4.4.1 writing to i/o port....................................................................................................... ................. 102 4.4.2 reading from i/o port ..................................................................................................... ............ 102 4.4.3 arithmetic operation of i/o port.......................................................................................... ......... 102 chapter 5 clock generator.................................................................................................. .. 103 5.1 clock generator functions ................................................................................................... . 103 5.2 clock generator configuration .............................................................................................. 1 03 5.3 registers controlling clock generator ................................................................................. 105 5.4 system clock oscillators .................................................................................................... ... 108 5.4.1 main system clock oscillator .............................................................................................. ......... 108
users manual u15075ej1v0um00 13 5.4.2 subsystem clock oscillator ................................................................................................ ......... 109 5.4.3 divider circuit ........................................................................................................... ................... 111 5.4.4 when no subsystem clock is used ........................................................................................... .. 111 5.5 clock generator operation ................................................................................................... ..112 5.6 changing setting of system clock and cpu clock..............................................................113 5.6.1 time required for switching between system clock and cpu clock ........................................... 113 5.6.2 switching between system clock and cpu clock ....................................................................... 114 chapter 6 16-bit timer ..................................................................................................... .............115 6.1 16-bit timer functions ...................................................................................................... ......115 6.2 16-bit timer configuration .................................................................................................. ....116 6.3 registers controlling 16-bit timer .........................................................................................1 19 6.4 16-bit timer operation...................................................................................................... .......123 6.4.1 operation as timer interrupt.............................................................................................. .......... 123 6.4.2 operation as timer output ................................................................................................. .......... 125 6.4.3 capture operation......................................................................................................... .............. 126 6.4.4 16-bit timer counter 90 readout ........................................................................................... ....... 127 6.4.5 buzzer output operation ................................................................................................... .......... 128 6.5 notes on using 16-bit timer ................................................................................................. ..129 chapter 7 8-bit timer ...................................................................................................... ..............131 7.1 8-bit timer functions ....................................................................................................... .......131 7.2 8-bit timer configuration ................................................................................................... .....132 7.3 registers controlling 8-bit timer ........................................................................................... 138 7.4 8-bit timer operation....................................................................................................... ........143 7.4.1 operation as 8-bit timer counter .......................................................................................... ....... 143 7.4.2 operation as 16-bit timer counter ......................................................................................... ...... 153 7.4.3 operation as carrier generator ............................................................................................ ....... 160 7.4.4 pwm free-running mode operation (timer 50) ............................................................................ 164 7.4.5 operation as pwm output (timer 60) ........................................................................................ .. 168 7.5 notes on using 8-bit timer .................................................................................................. ...170 chapter 8 watch timer ...................................................................................................... ..........171 8.1 watch timer functions....................................................................................................... .....171 8.2 watch timer configuration ................................................................................................... ..172 8.3 watch timer control register................................................................................................ .173 8.4 watch timer operation ....................................................................................................... .....174 8.4.1 operation as watch timer.................................................................................................. .......... 174 8.4.2 operation as interval timer ............................................................................................... .......... 174 chapter 9 watchdog timer................................................................................................... .....177 9.1 watchdog timer functions .................................................................................................... .177 9.2 watchdog timer configuration...............................................................................................1 78 9.3 watchdog timer control registers ........................................................................................179
14 users manual u15075ej1v0um00 9.4 watchdog timer operation .................................................................................................... 181 9.4.1 operation as watchdog timer............................................................................................... ....... 181 9.4.2 operation as interval timer............................................................................................... ........... 182 chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries)........................ 183 10.1 8-bit a/d converter functions .............................................................................................. . 183 10.2 8-bit a/d converter configuration......................................................................................... 1 83 10.3 8-bit a/d converter control registers .................................................................................. 186 10.4 8-bit a/d converter operation .............................................................................................. . 188 10.4.1 basic operation of 8-bit a/d converter ................................................................................... ..... 188 10.4.2 input voltage and conversion result...................................................................................... ...... 189 10.4.3 operation mode of 8-bit a/d converter .................................................................................... ... 191 10.5 cautions related to 8-bit a/d converter............................................................................... 192 chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries)...................... 197 11.1 10-bit a/d converter functions ............................................................................................. 197 11.2 10-bit a/d converter configuration....................................................................................... 19 7 11.3 10-bit a/d converter control registers ................................................................................ 200 11.4 10-bit a/d converter operation ............................................................................................. 202 11.4.1 basic operation of 10-bit a/d converter .................................................................................. .... 202 11.4.2 input voltage and conversion result...................................................................................... ...... 203 11.4.3 operation mode of 10-bit a/d converter ................................................................................... .. 205 11.5 cautions related to 10-bit a/d converter............................................................................. 206 chapter 12 serial interface 20 ............................................................................................ .. 211 12.1 serial interface 20 functions.............................................................................................. .... 211 12.2 serial interface 20 configuration .......................................................................................... . 211 12.3 serial interface 20 control registers..................................................................................... 2 15 12.4 serial interface 20 operation .............................................................................................. .... 222 12.4.1 operation stop mode ...................................................................................................... ............ 222 12.4.2 asynchronous serial interface (uart) mode ............................................................................. 224 12.4.3 3-wire serial i/o mode................................................................................................... .............. 237 chapter 13 lcd controller/driver....................................................................................... 247 13.1 lcd controller/driver functions ........................................................................................... 2 47 13.2 lcd controller/driver configuration ..................................................................................... 247 13.3 registers controlling lcd controller/driver ........................................................................ 249 13.4 setting lcd controller/driver .............................................................................................. .. 253 13.5 lcd display data memory.................................................................................................... .. 253 13.6 common and segment signals.............................................................................................. 254 13.7 display modes.............................................................................................................. ............ 256 13.7.1 three-time slot display example .......................................................................................... ....... 256 13.7.2 four-time slot display example ........................................................................................... ........ 259
users manual u15075ej1v0um00 15 chapter 14 interrupt functions............................................................................................. 263 14.1 interrupt function types ................................................................................................... ......263 14.2 interrupt sources and configuration .....................................................................................263 14.3 registers controlling interrupt function...............................................................................266 14.4 interrupt servicing operation .............................................................................................. ...272 14.4.1 non-maskable interrupt request acknowledgment operation ..................................................... 272 14.4.2 maskable interrupt request acknowledgment operation ............................................................. 274 14.4.3 multiple interrupt servicing............................................................................................. ............. 275 14.4.4 putting interrupt requests on hold....................................................................................... ........ 277 chapter 15 standby function ................................................................................................ ..279 15.1 standby function and configuration .....................................................................................279 15.1.1 standby function......................................................................................................... ................ 279 15.1.2 register controlling standby function.................................................................................... ...... 280 15.2 standby function operation ................................................................................................. ..281 15.2.1 halt mode ................................................................................................................ ................ 281 15.2.2 stop mode ................................................................................................................ ................ 284 chapter 16 reset function .................................................................................................. ......287 chapter 17 m m m m pd78f9436, 78f9456 ...................................................................................................291 17.1 flash memory programming ................................................................................................... 292 17.1.1 selecting communication mode............................................................................................. ..... 292 17.1.2 function of flash memory programming ..................................................................................... 293 17.1.3 flashpro iii connection example.......................................................................................... ....... 293 17.1.4 example of settings for flashpro iii (pg-fp3)............................................................................ 295 chapter 18 mask options.................................................................................................... ........297 chapter 19 instruction set ................................................................................................. ......299 19.1 operation.................................................................................................................. .................299 19.1.1 operand identifiers and description methods ............................................................................. 2 99 19.1.2 description of operation column........................................................................................ ...... 300 19.1.3 description of flag column............................................................................................. .......... 300 19.2 operation list ............................................................................................................. ..............301 19.3 instructions listed by addressing type................................................................................306 appendix a development tools ............................................................................................... 309 a.1 language processing software..............................................................................................31 1 a.2 flash memory writing tools .................................................................................................. .312 a.3 debugging tools ............................................................................................................. .........313 a.3.1 hardware .................................................................................................................. .................. 313 a.3.2 software .................................................................................................................. ................... 314
16 users manual u15075ej1v0um00 appendix b embedded software ............................................................................................. 31 5 appendix c register index.................................................................................................. ....... 317 c.1 register index (alphabetic order of register name) .......................................................... 317 c.2 register index (alphabetic order of register symbol) ....................................................... 319
users manual u15075ej1v0um00 17 list of figures (1/5) figure no. title page 2-1 pin input/output circuits ................................................................................................... ............................ 45 3-1 memory map ( m pd789425, 789435) ............................................................................................................. 4 7 3-2 memory map ( m pd789426, 789436) ............................................................................................................. 4 8 3-3 memory map ( m pd78f9436)..................................................................................................................... .... 49 3-4 memory map ( m pd789445, 789455) ............................................................................................................. 5 0 3-5 memory map ( m pd789446, 789456) ............................................................................................................. 5 1 3-6 memory map ( m pd78f9456)..................................................................................................................... .... 52 3-7 data memory addressing ( m pd789425, 789435) ......................................................................................... 55 3-8 data memory addressing ( m pd789426, 789436) ......................................................................................... 56 3-9 data memory addressing ( m pd78f9436) ..................................................................................................... 57 3-10 data memory addressing ( m pd789445, 789455) ......................................................................................... 58 3-11 data memory addressing ( m pd789446, 789456) ......................................................................................... 59 3-12 data memory addressing ( m pd78f9456) ..................................................................................................... 60 3-13 program counter configuration .............................................................................................. ...................... 61 3-14 program status word configuration .......................................................................................... ................... 61 3-15 stack pointer configuration ................................................................................................ .......................... 63 3-16 data to be saved to stack memory ........................................................................................... ................... 63 3-17 data to be restored from stack memory...................................................................................... ................ 63 3-18 general-purpose register configuration ..................................................................................... ................. 64 4-1 port types ( m pd789426, 789436 subseries) ............................................................................................... 77 4-2 port types ( m pd789446, 789456 subseries) ............................................................................................... 78 4-3 block diagram of p00 to p03 ................................................................................................. ....................... 81 4-4 block diagram of p10 and p11 ................................................................................................ ..................... 82 4-5 block diagram of p20........................................................................................................ ............................ 83 4-6 block diagram of p21 and p26 ................................................................................................ ..................... 84 4-7 block diagram of p22........................................................................................................ ............................ 85 4-8 block diagram of p23........................................................................................................ ............................ 86 4-9 block diagram of p24........................................................................................................ ............................ 87 4-10 block diagram of p25....................................................................................................... ............................. 88 4-11 block diagram of p30....................................................................................................... ............................. 89 4-12 block diagram of p31 to p33 ................................................................................................ ........................ 90 4-13 block diagram of p50 to p53 ................................................................................................ ........................ 91 4-14 block diagram of port 6 .................................................................................................... ............................ 92 4-15 block diagram of p70 to p72 ................................................................................................ ........................ 93 4-16 block diagram of p80, p81 .................................................................................................. ......................... 94 4-17 block diagram of p90 to p97 ................................................................................................ ........................ 95 4-18 format of port mode register ............................................................................................... ........................ 97 4-19 format of pull-up resistor option register 0 ............................................................................... ................ 98 4-20 format of pull-up resistor option register b2.............................................................................. ............... 99 4-21 format of pull-up resistor option register b3.............................................................................. ............... 99
18 users manual u15075ej1v0um00 list of figures (2/5) figure no. title page 4-22 format of pull-up resistor option register b7.............................................................................. ............. 100 4-23 format of pull-up resistor option register b8.............................................................................. ............. 100 4-24 format of pull-up resistor option register b9.............................................................................. ............. 101 5-1 block diagram of clock generator ............................................................................................ .................. 104 5-2 format of processor clock control register .................................................................................. ............. 105 5-3 format of suboscillation mode register ...................................................................................... ............... 106 5-4 format of subclock control register ......................................................................................... ................. 107 5-5 external circuit of main system clock oscillator ............................................................................ ............ 108 5-6 external circuit of subsystem clock oscillator .............................................................................. ............. 109 5-7 examples of incorrect resonator connection.................................................................................. ........... 110 5-8 switching between system clock and cpu clock................................................................................ ...... 114 6-1 block diagram of 16-bit timer............................................................................................... ...................... 117 6-2 format of 16-bit timer mode control register 90............................................................................. .......... 120 6-3 format of buzzer output control register 90 ................................................................................. ............ 121 6-4 format of port mode register 2 .............................................................................................. .................... 122 6-5 settings of 16-bit timer mode control register 90 for timer interrupt operation ...................................... 123 6-6 timing of timer interrupt operation ......................................................................................... ................... 124 6-7 settings of 16-bit timer mode control register 90 for timer output operation ......................................... 125 6-8 timer output timing......................................................................................................... ........................... 125 6-9 settings of 16-bit timer mode control register 90 for capture operation ................................................. 126 6-10 capture operation timing (both edges of cpt90 pin are specified) ........................................................ 126 6-11 16-bit timer counter 90 readout timing..................................................................................... ............... 127 6-12 settings of buzzer output control register 90 for buzzer output operation.............................................. 128 7-1 block diagram of timer 50 ................................................................................................... ....................... 133 7-2 block diagram of timer 60 ................................................................................................... ....................... 134 7-3 block diagram of output controller (timer 60) ............................................................................... ............ 135 7-4 format of 8-bit timer mode control register 50.............................................................................. ........... 139 7-5 format of 8-bit timer mode control register 60.............................................................................. ........... 141 7-6 format of carrier generator output control register 60 ...................................................................... ...... 142 7-7 format of port mode register 3 .............................................................................................. .................... 142 7-8 timing of interval timer operation with 8-bit resolution (basic operation) ............................................... 145 7-9 timing of interval timer operation with 8-bit resolution (when crn0 is set to 00h) ............................... 145 7-10 timing of interval timer operation with 8-bit resolution (when crn0 is set to ffh) ............................... 146 7-11 timing of interval timer operation with 8-bit resolution (when crn0 changes from n to m (n < m)) ..... 146 7-12 timing of interval timer operation with 8-bit resolution (when crn0 changes from n to m (n > m)) ..... 147 7-13 timing of interval timer operation with 8-bit resolution (when timer 60 match signal is selected for timer 50 count clock) ............................................................................................. ............... 148 7-14 timing of operation of external event counter with 8-bit resolution ....................................................... . 150 7-15 timing of square-wave output with 8-bit resolution ......................................................................... ........ 152
users manual u15075ej1v0um00 19 list of figures (3/5) figure no. title page 7-16 timing of interval timer operation with 16-bit resolution .................................................................. ........ 155 7-17 timing of external event counter operation with 16-bit resolution.......................................................... . 157 7-18 timing of square-wave output with 16-bit resolution ........................................................................ ....... 159 7-19 timing of carrier generator operation (when cr60 = n, crh60 = m (m > n)) ........................................ 161 7-20 timing of carrier generator operation (when cr60 = n, crh60 = m (m < n), phases of carrier clock and nrz60 are asynchronous) ........................................................................... 1 62 7-21 timing of carrier generator operation (when cr60 = crh60 = n) .......................................................... 163 7-22 operation timing in pwm free-running mode (when rising edge is selected) ...................................... 165 7-23 operation timing when overwriting cr50 (when rising edge is selected) ............................................. 165 7-24 operation timing in pwm free-running mode (when both edges are selected) .................................... 166 7-25 operation timing in pwm free-running mode (when both edges are selected) (when cr50 is overwritten) ..................................................................................................... .................. 167 7-26 pwm pulse generator mode timing (basic operation).......................................................................... .... 169 7-27 pwm output mode timing (when cr60 and crh60 are overwritten)...................................................... 169 7-28 start timing of 8-bit timer counter........................................................................................ ..................... 170 7-29 timing of operation as external event counter (8-bit resolution) ........................................................... .. 170 8-1 block diagram of watch timer................................................................................................ .................... 171 8-2 format of watch timer mode control register................................................................................. .......... 173 8-3 watch timer/interval timer operation timing ................................................................................. ........... 175 9-1 block diagram of watchdog timer............................................................................................. ................. 178 9-2 format of watchdog timer clock select register .............................................................................. ........ 179 9-3 format of watchdog timer mode register ...................................................................................... ........... 180 10-1 block diagram of 8-bit a/d converter....................................................................................... .................. 184 10-2 format of a/d converter mode register 0.................................................................................... .............. 186 10-3 format of analog input channel specification register 0.................................................................... ....... 187 10-4 basic operation of 8-bit a/d converter..................................................................................... .................. 189 10-5 relationship between analog input voltage and a/d conversion result................................................... 190 10-6 software-started a/d conversion ............................................................................................ ................... 191 10-7 how to reduce current consumption in standby mode.......................................................................... ... 192 10-8 conversion result read timing (if conversion result is undefined)......................................................... 1 93 10-9 conversion result read timing (if conversion result is normal) ............................................................. 193 10-10 analog input pin treatment................................................................................................ ......................... 194 10-11 a/d conversion end interrupt request generation timing .................................................................... .... 195 10-12 av dd pin handling.................................................................................................................. ..................... 195 11-1 block diagram of 10-bit a/d converter...................................................................................... ................. 198 11-2 format of a/d converter mode register 0.................................................................................... .............. 200 11-3 format of analog input channel specification register 0.................................................................... ....... 201 11-4 basic operation of 10-bit a/d converter.................................................................................... ................. 203
20 users manual u15075ej1v0um00 list of figures (4/5) figure no. title page 11-5 relationship between analog input voltage and a/d conversion result ................................................... 204 11-6 software-started a/d conversion ............................................................................................ ................... 205 11-7 how to reduce current consumption in standby mode.......................................................................... ... 206 11-8 conversion result read timing (if conversion result is undefined)......................................................... 2 07 11-9 conversion result read timing (if conversion result is normal)............................................................. . 207 11-10 analog input pin treatment................................................................................................ ......................... 208 11-11 a/d conversion end interrupt request generation timing.................................................................... ..... 209 11-12 av dd pin handling.................................................................................................................. ..................... 209 12-1 block diagram of serial interface 20....................................................................................... .................... 212 12-2 block diagram of baud rate generator 20 .................................................................................... ............. 213 12-3 format of serial operation mode register 20................................................................................ ............. 215 12-4 format of asynchronous serial interface mode register 20................................................................... .... 216 12-5 format of asynchronous serial interface status register 20 ................................................................. .... 218 12-6 format of baud rate generator control register 20 .......................................................................... ........ 219 12-7 format of asynchronous serial interface transmit/receive data.............................................................. . 231 12-8 asynchronous serial interface transmission completion interrupt timing................................................. 233 12-9 asynchronous serial interface reception completion interrupt timing ...................................................... 23 4 12-10 receive error timing...................................................................................................... ............................. 235 12-11 3-wire serial i/o mode timing ............................................................................................. ....................... 240 13-1 block diagram of lcd controller/driver..................................................................................... ................. 248 13-2 format of lcd display mode register 0...................................................................................... ............... 250 13-3 format of lcd clock control register 0 ..................................................................................... ................ 251 13-4 format of lcd voltage amplification control register 0 ..................................................................... ....... 252 13-5 relationship between lcd display data memory contents and segment/common outputs ( m pd789446, 789456 subseries) .................................................................................................... ............ 253 13-6 common signal waveforms.................................................................................................... .................... 255 13-7 voltages and phases of common and segment signals.......................................................................... .. 255 13-8 three-time slot lcd display pattern and electrode connections ............................................................. 2 56 13-9 example of connecting three-time slot lcd panel ............................................................................ ...... 257 13-10 three-time slot lcd drive waveform examples ............................................................................... ........ 258 13-11 four-time slot lcd display pattern and electrode connections .............................................................. . 259 13-12 example of connecting four-time slot lcd panel ............................................................................ ........ 260 13-13 four-time slot lcd drive waveform examples ................................................................................ ......... 261 14-1 basic configuration of interrupt function .................................................................................. .................. 265 14-2 format of interrupt request flag registers ................................................................................. ............... 267 14-3 format of interrupt mask flag registers .................................................................................... ................. 268 14-4 format of external interrupt mode register 0 ............................................................................... .............. 269 14-5 format of external interrupt mode register 1 ............................................................................... .............. 270 14-6 configuration of program status word....................................................................................... ................. 270
users manual u15075ej1v0um00 21 list of figures (5/5) figure no. title page 14-7 format of key return mode register 00...................................................................................... ............... 271 14-8 block diagram of falling edge detector ..................................................................................... ................ 271 14-9 flow from generation of non-maskable interrupt request to acknowledgment......................................... 273 14-10 timing of non-maskable interrupt request acknowledgment ................................................................... . 273 14-11 non-maskable interrupt request acknowledgment ............................................................................. ....... 273 14-12 interrupt request acknowledgment program algorithm ........................................................................ ..... 274 14-13 interrupt request acknowledgment timing (example: mov a, r) .............................................................. 2 75 14-14 interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execution) ...................................................................................... .......... 275 14-15 example of multiple interrupts............................................................................................ ......................... 276 15-1 format of oscillation stabilization time select register................................................................... .......... 280 15-2 releasing halt mode by interrupt ........................................................................................... .................. 282 15-3 releasing halt mode by reset input ......................................................................................... ............ 283 15-4 releasing stop mode by interrupt ........................................................................................... ................. 285 15-5 releasing stop mode by reset input......................................................................................... ............ 286 16-1 block diagram of reset function............................................................................................ .................... 287 16-2 reset timing by reset input ................................................................................................ .................... 288 16-3 reset timing by overflow in watchdog timer ................................................................................. ........... 288 16-4 reset timing by reset input in stop mode ................................................................................... ......... 288 17-1 communication mode selection format ........................................................................................ ............. 292 17-2 flashpro iii connection example in 3-wire serial i/o mode.................................................................. ..... 293 17-3 flashpro iii connection example in uart mode............................................................................... ......... 294 a-1 development tools ........................................................................................................... .......................... 310
22 users manual u15075ej1v0um00 list of tables (1/2) table no. title page 2-1 types of pin input/output circuits.......................................................................................... ....................... 44 3-1 internal rom capacity ....................................................................................................... ........................... 53 3-2 vector table ................................................................................................................ .................................. 53 3-3 lcd display ram capacity.................................................................................................... ....................... 54 3-4 special function register list.............................................................................................. ......................... 66 4-1 port functions .............................................................................................................. ................................. 79 4-2 configuration of port ....................................................................................................... .............................. 80 4-3 port mode register and output latch settings when using alternate functions ........................................ 98 5-1 configuration of clock generator............................................................................................ .................... 103 5-2 maximum time required for switching cpu clock ............................................................................... ..... 113 6-1 16-bit timer configuration .................................................................................................. ........................ 116 6-2 interval time of 16-bit timer ............................................................................................... ........................ 123 6-3 settings of capture edge .................................................................................................... ........................ 126 6-4 buzzer frequency of 16-bit timer............................................................................................ ................... 128 7-1 operation modes............................................................................................................. ............................ 131 7-2 8-bit timer configuration ................................................................................................... ......................... 132 7-3 interval time of timer 50 ................................................................................................... ......................... 144 7-4 interval time of timer 60 ................................................................................................... ......................... 144 7-5 square-wave output range of timer 50 (during f x = 5.0 mhz operation) ................................................ 151 7-6 square-wave output range of timer 60 (during f x = 5.0 mhz operation) ................................................ 152 7-7 interval time with 16-bit resolution (during f x = 5.0 mhz operation) ........................................................ 154 7-8 square-wave output range with 16-bit resolution (during f x = 5.0 mhz operation)................................ 158 8-1 interval generated using the interval timer ................................................................................. .............. 172 8-2 watch timer configuration................................................................................................... ....................... 172 8-3 interval time of interval timer............................................................................................. ........................ 174 9-1 watchdog timer runaway detector time........................................................................................ ........... 177 9-2 interval time............................................................................................................... ................................. 177 9-3 configuration of watchdog timer............................................................................................. ................... 178 9-4 watchdog timer runaway detection time ....................................................................................... .......... 181 9-5 interval time of interval timer............................................................................................. ........................ 182 10-1 configuration of 8-bit a/d converter ....................................................................................... .................... 183 11-1 configuration of 10-bit a/d converter ...................................................................................... ................... 197
users manual u15075ej1v0um00 23 list of tables (2/2) table no. title page 12-1 configuration of serial interface 20....................................................................................... ...................... 211 12-2 serial interface 20 operating mode settings ................................................................................ .............. 217 12-3 example of relationships between system clock and baud rate............................................................. 220 12-4 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h)....... 221 12-5 example of relationships between system clock and baud rate............................................................. 229 12-6 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h)....... 230 12-7 receive error causes ....................................................................................................... .......................... 235 13-1 number of segment outputs and maximum number of pixels................................................................... 24 7 13-2 configuration of lcd controller/driver..................................................................................... ................... 247 13-3 frame frequencies (hz) ..................................................................................................... ........................ 251 13-4 com signals ................................................................................................................ ............................... 254 13-5 lcd drive voltage.......................................................................................................... ............................. 254 13-6 select and deselect voltages (com0 to com2) ................................................................................ ........ 256 13-7 select and deselect voltages (com0 to com3) ................................................................................ ........ 259 14-1 interrupt source list...................................................................................................... .............................. 264 14-2 flags corresponding to interrupt request signal name....................................................................... ...... 266 14-3 time from generation of maskable interrupt request to servicing ............................................................ 274 15-1 halt mode operating status ................................................................................................. .................... 281 15-2 operation after releasing halt mode........................................................................................ ............... 283 15-3 stop mode operating status................................................................................................. .................... 284 15-4 operation after releasing stop mode ........................................................................................ .............. 286 16-1 hardware status after reset................................................................................................ ....................... 289 17-1 differences between m pd78f9436, 78f9456 and mask rom versions.................................................... 291 17-2 communication mode ......................................................................................................... ........................ 292 17-3 functions of flash memory programming ...................................................................................... ............ 293 17-4 example of settings for pg-fp3 ............................................................................................. .................... 295 18-1 selection of mask option for pins .......................................................................................... ..................... 297 19-1 operand identifiers and description methods ................................................................................ ............. 299
24 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 25 chapter 1 general 1.1 features ? rom and ram capacities item data memory part number program memory (rom) internal high-speed ram lcd display ram m pd789425, 789435 8 kb m pd789426, 789436 mask rom 16 kb m pd78f9436 flash memory 16 kb 5 bytes m pd789445, 789455 12 kb m pd789446, 789456 mask rom m pd78f9456 flash memory 16 kb 512 bytes 15 bytes ? minimum instruction execution time can be changed from high-speed (0.4 m s: @ 5.0 mhz operation with main system clock) to ultra-low-speed (122 m s: @ 32.768 khz operation with subsystem clock) ? i/o ports: 40 ( m pd789426, 789436 subseries) 30 ( m pd789446, 789456 subseries) ? timer: 5 channels ? 16-bit timer: 1 channel ? 8-bit timer: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel ? a/d converter: 8-bit resolution: 6 channels ( m pd789426, 789446 subseries) 10-bit resolution: 6 channels ( m pd789436, 789456 subseries) ? serial interface: 1 channel ? lcd controller/driver segment signals: 5, common signals: 4 ( m pd789426, 789436 subseries) segment signals: 15, common signals: 4 ( m pd789446, 789456 subseries) ? vectored interrupt sources: 15 ? power supply voltage: v dd = 1.8 to 5.5 v ? operating ambient temperature: t a = C40 to +85 c 1.2 applications portable audio, cameras, healthcare equipment, etc.
chapter 1 general 26 users manual u15075ej1v0um00 1.3 ordering information part number package internal rom m pd789425gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789426gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789435gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789436gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789445gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789446gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789455gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd789456gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom m pd78f9436gk-9et 64-pin plastic tqfp (12 12 mm) flash memory m pd78f9456gk-9et 64-pin plastic tqfp (12 12 mm) flash memory remark indicates rom code suffix.
chapter 1 general users manual u15075ej1v0um00 27 1.4 pin configuration (top view) 1.4.1 pin configuration of m m m m pd789426, 789436 subseries (top view) 64-pin plastic tqfp (fine pitch) (12 12) m pd789425gk- -9et m pd789426gk- -9et m pd789435gk- -9et m pd789436gk- -9et m pd78f9436gk-9et 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 p51 p52 p53 ic(v pp ) xt1 xt2 v dd v ss x1 x2 reset p00/kr0 p01/kr1 p02/kr2 p03/kr3 32 caph capl v lc0 v lc1 v lc2 com0 com1 com2 com3 s0 s1 s2 s3 s4 p90 p91 p62/ani2 p63/ani3 p64/ani4 p65/ani5 av dd p72 p71 p70 p81 p80 p97 p96 p95 p94 p93 p92 p20 p21/bzo90 p22/ss20 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to90 p30/intp0/cpt90 p31/intp1/to50/tmi60 p32/intp2/to60 p33/intp3/to61 p10 p11 av ss p60/ani0 p61/ani1 cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . remark the parenthesized values apply to the m pd78f9436.
chapter 1 general 28 users manual u15075ej1v0um00 1.4.2 pin configuration of m m m m pd789446, 789456 subseries (top view) 64-pin plastic tqfp (fine pitch) (12 12) m pd789445gk- -9et m pd789446gk- -9et m pd789455gk- -9et m pd789456gk- -9et m pd78f9456gk-9et 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 p51 p52 p53 ic(v pp ) xt1 xt2 v dd v ss x1 x2 reset p00/kr0 p01/kr1 p02/kr2 p03/kr3 32 caph capl v lc0 v lc1 v lc2 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 p62/ani2 p63/ani3 p64/ani4 p65/ani5 av dd p72 p71 p70 s14 s13 s12 s11 s10 s9 s8 s7 p20 p21/bzo90 p22/ss20 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to90 p30/intp0/cpt90 p31/intp1/to50/tmi60 p32/intp2/to60 p33/intp3/to61 p10 p11 av ss p60/ani0 p61/ani1 cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . remark the parenthesized values apply to the m pd78f9456.
chapter 1 general users manual u15075ej1v0um00 29 ani0 to ani5: analog input p90 to p97 note 1 :port 9 asck20: asynchronous serial input reset: reset av dd : analog power supply rxd20: receive data av ss : analog ground ss20: serial chip select bzo90: buzzer output s0 to s4, s5 to s14 note 2 : segment output caph, capl: lcd power supply capacitance control sck20: serial clock com0 to com3: common output si20: serial input cpt90: capture trigger input so20: serial output ic: internally connected tmi60: timer input intp0 to intp3: external interrupt input to90, to50, to60, kr0 to kr3: key return to61: timer output p00 to p03: port 0 txd20: transmit data p10, p11: port 1 v dd : power supply p20 to p26: port 2 v lc0 to v lc2 : lcd power supply p30 to p33: port 3 v pp : programming power supply p50 to p53: port 5 v ss : ground p60 to p65: port 6 x1, x2: crystal (main system clock) p70 to p72: port 7 xt1, xt2: crystal (subsystem clock) p80, p81 note 1 :port 8 notes 1. m pd789426, 789436 subseries only 2. m pd789446, 789456 subseries only
chapter 1 general 30 users manual u15075ej1v0um00 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. products under development products in mass production pd789014 small-scale package, general-purpose applications 78k/0s series 28 -pin pd789014 with enhanced timer and increased rom, ram capacity on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock lcd drive inverter control 44 -pin pd789842 on-chip inverter controller and uart assp 80 -pin 80 -pin pd789446 pd789456 pd789436 pd789417a pd789407a pd789426 pd789306 pd789316 pd789426 with enhanced a/d pd789446 with enhanced a/d converter a/d converter and resistance division type lcd (28 4) a/d converter and on-chip voltage booster type lcd (15 4) pd789407a with enhanced a/d converter a/d converter and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 on-chip voltage booster type lcd (24 4) 64 -pin 64 -pin 64 -pin 64 -pin 64 -pin 64 -pin pd789146 pd789156 44 -pin small-scale package, general-purpose applications and a/d converter 44 -pin 30 -pin 30 -pin 30 -pin 30 -pin pd789124a pd789134a pd789177 pd789167 30 -pin 30 -pin pd789104a pd789114a pd789167 with enhanced a/d converter pd789104a with enhanced timer pd789124a with enhanced a/d converter rc oscillation version of the pd789104a pd789104a with enhanced a/d converter pd789026 with added a/d converter and multiplier pd789104a with added eeprom tm pd789146 with enhanced a/d converter pd789177y pd789167y y subseries products support smb. dot lcd drive 20 -pin pd789860 pd789840 44 -pin 44 -pin pd789800 20 -pin pd789861 for keyless entry, on-chip poc and key return circuit for keypad, on-chip poc for pc keyboard, on-chip usb function rc oscillation version of the pd789860 52 -pin 52 -pin for remote controller, with sio and resistance division type lcd for remote controller, with a/d converter and on-chip voltage booster type lcd 88 -pin pd789830 pd789835 144 -pin segments: 40, commons: 16 segment/common outputs: 96 42-/44 -pin 44 -pin pd789046 pd789074 pd789026 30 -pin pd789026 with enhanced timer vfd drive 52 -pin pd789871 total display outputs: 25 pd789488 a/d converter and on-chip voltage booster type lcd (28 4) 80 -pin pd789488 with added remote control receiver and resistance division type lcd 80 -pin pd789327 pd789803 64 -pin pd789467 pd789477 for pc keyboard, on-chip usb hub function m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m m
chapter 1 general users manual u15075ej1v0um00 31 the major functional differences among the subseries are listed below. v dd function subseries name rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks m pd789046 16 k 1 ch m pd789026 4 k to 16 k 34 m pd789074 2 k to 8 k 1 ch 1 ch 24 small-scale package, general- purpose applications m pd789014 2 k to 4 k 2 ch - - -- 1 ch (uart: 1 ch) 22 - m pd789177 - 8 ch m pd789167 16 k to 24 k 3 ch 1 ch 8 ch - 31 - m pd789156 - 4 ch m pd789146 8 k to 16 k 4 ch - on-chip eeprom m pd789134a - 4 ch m pd789124a 4 ch - rc-oscillation version m pd789114a - 4 ch small-scale package, general- purpose applications and a/d converter m pd789104a 2 k to 8 k 1 ch 1 ch - 1 ch 4 ch - 1 ch (uart: 1 ch) 20 1.8 v - inverter control m pd789842 8 k to 16 k 3 ch note 1 ch 1 ch 8 ch - 1 ch (uart: 1 ch) 30 4.0 v - vfd drive m pd789871 4 k to 8 k 3 ch C 1 ch 1 ch C C 1 ch 33 2.7 v C m pd789488 32 k 8 ch 2 ch (uart: 1 ch) 45 m pd789417a - 7 ch m pd789407a 12 k to 24 k 3 ch 7 ch - 43 m pd789456 C 6 ch m pd789446 6 ch C 30 m pd789436 C 6 ch m pd789426 12 k to 16 k 6 ch 1 ch (uart: 1 ch) 40 - m pd789316 rc-oscillation version lcd drive m pd789306 8 k to 16 k 2 ch 1 ch 1 ch 1 ch C C 2 ch (uart: 1 ch) 23 1.8 v C m pd789835 24 k to 60 k 6 ch C 3 ch 28 1.8 v dot lcd drive m pd789830 24 k 1 ch 1 ch 1 ch 1 ch C C1 ch (uart: 1 ch) 30 2.7 v - m pd789477 24 k 3 ch 1 ch 8 ch 2 ch (uart: 1 ch) 45 m pd789467 1 ch C 18 m pd789327 4 k to 24 k 1 ch 1 ch 21 1.8 v on-chip lcd m pd789800 C 2 ch (usb: 1 ch) 31 4.0 v m pd789840 8 k 4 ch 1 ch 29 2.8 v - m pd789861 rc-oscillation version, on-chip eeprom assp m pd789860 4 k 2 ch C - 1 ch - C C 14 1.8 v on-chip eeprom note 10-bit timer: 1 channel
chapter 1 general 32 users manual u15075ej1v0um00 1.6 block diagram 1.6.1 block diagram of m m m m pd789426, 789436 subseries v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory) to50/tmi60/ p31 8-bit timer 50 p00 to p03 port 0 p10, p11 port 1 p20 to p26 port 2 p30 to p33 port 3 tmi60/to50/ p31 16-bit timer 90 watch timer watchdog timer to90/p26 s0 to s4 com0 to com3 ram ram space for lcd data 8-bit timer/event counter 60 cascaded 16-bit timer/ event counter to60/p32 cpt90/p30 v lc0 to v lc2 caph capl lcd controller driver p50 to p53 port 5 system control reset x1 x2 xt1 xt2 interrupt control intp0/p30 intp1/p31 intp2/p32 intp3/p33 kr0/p00 to kr3/p03 to61/p33 bzo90/p21 serial iinterface 20 sck20/asck20/p23 si20/rxd20/p25 so20/txd20/p24 ss20/p22 a/d converter ani0/p60 to ani5/p65 av ss av dd p70 to p72 port 7 p60 to p65 port 6 p80, p81 port 8 p90 to p97 port 9 remarks 1. the internal rom capacity varies depending on the product. 2. the parenthesized values apply to the m pd78f9436.
chapter 1 general users manual u15075ej1v0um00 33 1.6.2 block diagram of m m m m pd789446, 789456 subseries remarks 1. the internal rom capacity varies depending on the product. 2. the parenthesized values apply to the m pd78f9456. v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory) to50/tmi60/ p31 8-bit timer 50 p00 to p03 port 0 p10, p11 port 1 p20 to p26 port 2 p30 to p33 port 3 tmi60/to50/ p31 16-bit timer 90 watch timer watchdog timer to90/p26 s0 to s4 com0 to com3 ram ram space for lcd data 8-bit timer/event counter 60 cascaded 16-bit timer/ event counter to60/p32 cpt90/p30 v lc0 to v lc2 caph capl lcd controller driver p50 to p53 port 5 system control reset x1 x2 xt1 xt2 interrupt control intp0/p30 intp1/p31 intp2/p32 intp3/p33 kr0/p00 to kr3/p03 to61/p33 bzo90/p21 serial iinterface 20 sck20/asck20/p23 si20/rxd20/p25 so20/txd20/p24 ss20/p22 a/d converter ani0/p60 to ani5/p65 av ss av dd p70 to p72 port 7 p60 to p65 port 6 p80, p81 port 8 p90 to p97 port 9
chapter 1 general 34 users manual u15075ej1v0um00 1.7 overview of functions item m pd789425, 789435 m pd789426, 789436 m pd78f9436 m pd789445, 789455 m pd789446, 789456 m pd78f9456 mask rom flash memory mask rom flash memory rom 12 kb 16 kb 12 kb 16 kb high-speed ram 512 bytes internal memory lcd display ram 5 bytes 15 bytes minimum instruction execution time ? 0.4 m s/1.6 m s (@ 5.0 mhz operation with main system clock) ? 122 m s (@ 32.768 khz operation with sub system clock) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) i/o ports total: 40 ? cmos i/o: 30 ? cmos input: 6 ? n-ch open-drain: 4 total: 30 ? cmos i/o: 20 ? cmos input: 6 ? n-ch open-drain: 4 timers ? 16-bit timer: 1 channel ? 8-bit timer: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel a/d converter ? 8-bit resolution 6 channels ( m pd789426, 789446 subseries) ? 10-bit resolution 6 channels ( m pd789436, 789456 subseries) serial interfaces switchable between 3-wire serial i/o mode and uart mode: 1 channel lcd controller/driver ? segment signal outputs: 5 max. ? common signal outputs: 4 max. ? segment signal outputs: 15 max. ? common signal outputs: 4 max. maskable internal: 9, external: 5 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40 to + 85c package 64-pin plastic tqfp (fine pitch) (12 12)
chapter 1 general users manual u15075ej1v0um00 35 an outline of the timer is shown below. 16-bit timer 8Cbit timer 50 8-bit timer 60 watch timer watchdog timer interval timer C 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter C C 1 channel C C timer outputs 1 1 2 C C square-wave outputs C12CC capture 1 input C C C C function interrupt sources 11111 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or interval timer function.
36 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 37 chapter 2 pin functions 2.1 list of pin functions (1) port pins (1/2) pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0) or key return mode register 00 (krm00). input kr0 to kr3 p10 to p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0). input C p20 C p21 bzo90 p22 ss20 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b2 (pub2). input to90 p30 intp0/cpt90 p31 intp1/to50/ tmi60 p32 intp2/to60 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b3 (pub3). input intp3/to61 p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by the mask option. input - p60 to p65 input port 6. 6-bit input port. input ani0 to ani5 p70 to p72 i/o port 7. 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b7 (pub7). input -
chapter 2 pin functions 38 users manual u15075ej1v0um00 (1) port pins (2/2) pin name i/o function after reset alternate function p80, p81 note i/o port 8. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b8 (pub8). input - p90 to p97 note i/o port 9. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b9 (pub9). input - note m pd789426, 789436 subseries only
chapter 2 pin functions users manual u15075ej1v0um00 39 (2) non-port pins pin name i/o function after reset alternate function intp0 p30/cpt90 intp1 p31/to50/tmi60 intp2 p32/to60 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33/to61 kr0 to kr3 input key return signal detection input p00 to p03 ss20 input serial interface (sio20) chip select input p22 sck20 i/o serial interface 20 serial clock input/output input p23/asck20 si20 input serial interface 20 of sio20 serial data input input p25/rxd20 so20 output serial interface 20 of sio20 serial data output input p24/txd20 asck20 input serial clock input for asynchronous serial interface input p23/sck20 rxd20 input serial data input for asynchronous serial interface input p25/si20 txd20 output serial data output for asynchronous serial interface input p24/so20 to90 output 16-bit timer (tm90) output input p26 cpt90 input capture edge input input p30/intp0 to50 output 8-bit timer (tm50) output input p31/intp1/tmi40 to60 output input p32/intp2 to61 output 8-bit timer (tm60) output input p33/intp33 tmi60 input external count clock input to timer 40 input p31/intp1/to50 ani0 to ani5 input a/d converter analog input input p60 to p65 s0 to s4 output output ? - ? s5 to s14 note output lcd controller/driver segment signal output output ? - ? com0 to com3 output lcd controller/driver common signal output output - v lc0 to v lc2 - lcd driving voltage - ? - ? caph - - ? - ? capl - capacitor connection pin for lcd drive - ? - ? x1 input - ? - ? x2 - connecting crystal resonator for main system clock oscillation - ? - ? xt1 input - ? - ? xt2 - connecting crystal resonator for sub system clock oscillation - ? - ? reset input system reset input input ? - ? v dd - positive power supply - ? - ? v ss - ground potential - ? - ? av dd - a/d converter analog potential - av ss - a/d converter analog ground potential - ? - ? ic - internally connected. connect directly to v ss . - ? - ? v pp - sets flash memory programming mode. applies high voltage when a program is written or verified. connect directly to v ss in normal operation mode. - ? - ? note m pd789446, 789456 subseries only
chapter 2 pin functions 40 users manual u15075ej1v0um00 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port. in addition, these pins enable key return signal detection. port 0 can be specified in the following operation modes in 1-bit units. (1) port mode these pins constitute a 4-bit i/o port and can be set in the input or output port mode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. (2) control mode in this mode, p00 to p03 function as key return signal detection pins (kr0 to kr3). 2.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set in the input or output port mode in 1-bit units by port mode register 1 (pm1). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. 2.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port. in addition, these pins enable buzzer output, timer output, serial interface data i/o, and serial clock i/o. port 2 can be specified in the following operation modes in 1-bit units. (1) port mode in this mode, p20 to p26 function as a 7-bit i/o port. port 2 can be set in the input or output port mode in 1- bit units by port mode register 2 (pm2). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b2 (pub2) in 1-bit units. (2) control mode in this mode, p20 to p26 function as the buzzer output, timer output, serial interface data i/o, and serial clock i/o. (a) buzzer output this is the buzzer output pin of 16-bit timer 90. (b) to90 this is the timer output pin of 16-bit timer 90. (c) si20, so20 these are the serial data i/o pins of the serial interface. (d) sck20 this is the serial clock i/o pin of the serial interface. (e) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface.
chapter 2 pin functions users manual u15075ej1v0um00 41 (f) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using p20 to p26 as serial interface pins, the i/o mode and output latch must be set according to the functions to be used. for the details of the setting, refer to table 12-2 settings of serial interface 20 operating mode. 2.2.4 p30 to p33 (port 3) these pins constitute a 4-bit i/o port. in addition, they also function as timer i/o and external interrupt input. port 3 can be specified in the following operation mode in 1-bit units. (1) port mode in this mode, p30 to p33 functions as a 4-bit i/o port. port 3 can be set in the input or output port mode in 1-bit units by port mode register 3 (pm3). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b3 (pub3) in 1-bit units. (2) control mode in this mode, p30 to p33 function as timer i/o and external interrupt input. (a) tmi60 this is the external clock input pin to timer 60. (b) to50, to60, to61 these are the timer output pins of timer 50 and timer 60 (c) cpt90 this is the capture edge input pin of 16-bit timer 90. (d) intp0 to intp3 these are external interrupt input pins for which valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.5 p50 to p53 (port 5) these pins function as a 4-bit n-ch open-drain i/o port. port 5 can be set in the input or output port mode in 1-bit units by port mode register 5 (pm5). in the mask rom version, use of an on-chip pull-up resistor can be specified by a mask option. 2.2.6 p60 to p65 (port 6) this is a 6-bit input-only port. in addition to a general-purpose input port function, it has an a/d converter input function. (1) port mode in this mode, p60 to p65 function as 6-bit input-only port. (2) control mode in this mode, p60 to p65 function as analog inputs (ani0 to ani5) of a/d converter.
chapter 2 pin functions 42 users manual u15075ej1v0um00 2.2.7 p70 to p72 (port 7) these pins constitute a 3-bit i/o port. port 7 can be set in the input or output mode in 1-bit units by port mode register 7 (pm7). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b7 (pub7) in port units. 2.2.8 p80, p81 (port 8) note these pins constitute a 2-bit i/o port. port 8 can be set in the input or output mode in 1-bit units by port mode register 8 (pm8). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b8 (pub8) in port units. note only the m pd789426 and m pd789436 subseries. 2.2.9 p90 to p97 (port 9) note these pins constitute an 8-bit i/o port. port 9 can be set in the input or output mode in 1-bit units by port mode register 9 (pm9). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b9 (pub9) in port units. note only the m pd789426 and m pd789436 subseries. 2.2.10 s0 to s14 note these pins are segment signal output pins for the lcd controller/driver. note s0 to s4 in the case of the m pd789426 and 789436 subseries 2.2.11 com0 to com3 these pins are common signal output pins for the lcd controller/driver. 2.2.12 v lc0 to v lc2 these pins are power supply voltage pins to drive the lcd. 2.2.13 caph, capl these pins are capacitor connection pins to drive the lcd. 2.2.14 reset this pin inputs an active-low system reset signal. 2.2.15 x1, x2 these pins are used to connect a crystal resonator for main system clock oscillation. to supply an external clock, input the clock to x1 and input the inverted signal to x2. 2.2.16 xt1, xt2 these pins are used to connect a crystal resonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2.
chapter 2 pin functions users manual u15075ej1v0um00 43 2.2.17 v dd this is the positive power supply pin. 2.2.18 v ss this is the ground pin. 2.2.19 v pp ( m m m m pd78f9436, 78f9456 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. directly connect this pin to v ss in the normal operation mode. 2.2.20 ic (mask rom version only) the ic (internally connected) pin is used to set the m pd789426, 789436, 789446, and 789456 subseries in the test mode before shipment. in the normal operation mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is generated between the ic pin and v ss pin due to a long wiring length, or an external noise superimposed on the ic pin, the user program may not run correctly. directly connect the ic pin to the v ss pin. v ss ic keep short
chapter 2 pin functions 44 users manual u15075ej1v0um00 2.3 pin input/output circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the input/output circuit configuration of each type, see figure 2-1. table 2-1. types of pin input/output circuits pin name i/o circuit type i/o recommended connection of unused pins p00/kr0 to p03/kr3 8-a p10, p11 5-a p20 p21/bzo90 p22/ss20 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to90 input: independently connect to v dd or v ss via a resistor. output: leave open. p30/inpt0/cpt90 p31/inpt1/to50/tmi60 p32/inpt2/to60 p33/inpt3/to61 8-a input: independently connect to v ss via a resistor. output: leave open. p50 to p53 (mask rom version) 13-w p50 to p53 (flash memory version) 13-v i/o input: independently connect to v dd via a resistor. output: leave open. p60/ani0 to p65/ani5 9-c input connect directly to v dd or v ss . p70 to p72 p80, p81 note 1 p90 to p97 note 1 5-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. s0 to s4 note 1 s0 to s14 note 2 17 output com0 to com3 18 v lc0 to v lc2 caph, capl ? - ? leave open. xt1 input c onnect to v ss . xt2 leave open. av ss connect to v ss . av dd - - connect to v dd . reset 2 input - ic v pp - ? - ? connect directly to v ss . notes 1. when using the m pd789426 and 789436 subseries 2. when using the m pd789446 and 789456 subseries
chapter 2 pin functions users manual u15075ej1v0um00 45 figure 2-1. pin input/output circuits type 2 type 13-v schmitt-triggered input with hysteresis characteristics in v ss output data output disable in/out n-ch middle-voltage input buffer input enable type 5-a type 13-w pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch v ss v ss output data output disable in/out v dd n-ch middle-voltage input buffer input enable pull-up resistor (mask option) type 8-a type 17 pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss p-ch p-ch v lc0 v lc1 n-ch p-ch n-ch v lc2 seg data p-ch out n-ch n-ch type 9-c type 18 in comparator + v ref (threshold voltage) av ss p-ch n-ch input enable - com data out p-ch p-ch v lc0 v lc1 n-ch v lc2 p-ch n-ch n-ch p-ch n-ch n-ch p-ch
46 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 47 chapter 3 cpu architecture 3.1 memory space the m pd789426, 789436, 789446, and 789456 subseries can access 64 kb of memory space. figures 3-1 through 3-6 show the memory maps. figure 3-1. memory map ( m m m m pd789425, 789435) special function registers 256 8 bits internal high-speed ram 512 8 bits lcd display ram 5 4 bits reserved reserved internal rom 12288 8 bits ffffh ff00h feffh fd00h fcffh fa00h f9ffh 0000h program memory space data memory space 2fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area fa05h fa04h 3000h 2fffh
chapter 3 cpu architecture 48 users manual u15075ej1v0um00 figure 3-2. memory map ( m m m m pd789426, 789436) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa05h fa04h 4000h 3fffh
chapter 3 cpu architecture users manual u15075ej1v0um00 49 figure 3-3. memory map ( m m m m pd78f9436) special function registers 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa05h fa04h 4000h 3fffh
chapter 3 cpu architecture 50 users manual u15075ej1v0um00 figure 3-4. memory map ( m m m m pd789445, 789455) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh ff00h feffh 0000h program memory space data memory space 2fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa0fh fa0eh 3000h 2fffh
chapter 3 cpu architecture users manual u15075ej1v0um00 51 figure 3-5. memory map ( m m m m pd789446, 789456) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa0fh fa0eh 4000h 3fffh
chapter 3 cpu architecture 52 users manual u15075ej1v0um00 figure 3-6. memory map ( m m m m pd78f9456) special function registers 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa0fh fa0eh 4000h 3fffh
chapter 3 cpu architecture users manual u15075ej1v0um00 53 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the m pd789426, 789436, 789446, and 789456 subseries provide internal rom (or flash memory) with the following capacity for each product. table 3-1. internal rom capacity part number internal rom structure capacity m pd789425, 789435, 789445, 789455 12288 8 bits m pd789426, 789436, 789446, 789456 mask rom 16384 8 bits m pd78f9436, 78f9456 flash memory 16384 8 bits the following areas are allocated to the internal program memory space. (1) vector table area the 34-byte area of addresses 0000h to 0021h is reserved as a vector table area. this area stores program start addresses to be used when branching by the reset input or an interrupt request generation. of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0014h intwti 0004h intwdt 0016h inttm90 0006h intp0 0018h inttm50 0008h intp1 001ah inttm60 000ah intp2 001ch intad0 000ch intp3 001eh intwt 000eh intsr20/intcsi20 0020h intkr00 0012h intst20 (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh.
chapter 3 cpu architecture 54 users manual u15075ej1v0um00 3.1.2 internal data memory (internal high-speed ram) space the m pd789426, 789436, 789446, and 789456 subseries products incorporate the following ram. (1) internal high-speed ram internal high-speed ram is incorporated in the area between fd00h and feffh. the internal high-speed ram is also used as a stack. (2) lcd display ram lcd display ram is incorporated. the lcd display ram can also be used as ordinary ram. each subseries incorporates lcd display ram with the following capacity. table 3-3. lcd display ram capacity subseries name area capacity m pd789426, 789436 subseries fa00h to fa04h 5 4 bits m pd789446, 789456 subseries fa00h to fa0eh 15 4 bits 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocated in the area between ff00h to ffffh (see table 3-4 ).
chapter 3 cpu architecture users manual u15075ej1v0um00 55 3.1.4 data memory addressing the m pd789426, 789436, 789446, and 789456 subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. at the addresses corresponding to data memory area (fd00h to ffffh) especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available. figures 3-7 through 3-12 show the data memory addressing modes. figure 3-7. data memory addressing ( m m m m pd789425, 789435) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh 0000h direct adressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh 3000h 2fffh fa05h fa04h
chapter 3 cpu architecture 56 users manual u15075ej1v0um00 figure 3-8. data memory addressing ( m m m m pd789426, 789436) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa05h fa04h
chapter 3 cpu architecture users manual u15075ej1v0um00 57 figure 3-9. data memory addressing ( m m m m pd78f9436) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa05h fa04h
chapter 3 cpu architecture 58 users manual u15075ej1v0um00 figure 3-10. data memory addressing ( m m m m pd789445, 789455) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh 3000h 2fffh fa0fh fa0eh
chapter 3 cpu architecture users manual u15075ej1v0um00 59 figure 3-11. data memory addressing ( m m m m pd789446, 789456) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa0fh fa0eh
chapter 3 cpu architecture 60 users manual u15075ej1v0um00 figure 3-12. data memory addressing ( m m m m pd78f9456) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa0fh fa0eh
chapter 3 cpu architecture users manual u15075ej1v0um00 61 3.2 processor registers the m pd789426, 789436, 789446, and 789456 subseries provide the following on-chip processor registers. 3.2.1 control registers the control registers contain special functions to control the program sequence statuses and stack memory. the program counter, program status word, and stack pointer are control registers. (1) program counter (pc) the program counter is a 16-bit register that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data or register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-13. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. the program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the reti and pop psw instructions. reset input sets psw to 02h. figure 3-14. program status word configuration 70 ie z 0 ac 0 0 1 cy psw
chapter 3 cpu architecture 62 users manual u15075ej1v0um00 (a) interrupt enable flag (ie) this flag controls interrupt request acknowledgement operations of the cpu. when 0, ie is set to the interrupt disable status (di), and interrupt requests other than non-maskable interrupt are all disabled. when 1, ie is set to the interrupt enable status (ei). interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
chapter 3 cpu architecture users manual u15075ej1v0um00 63 (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-15. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 3-16 and 3-17. caution since reset input makes the sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-16. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 higher register pairs figure 3-17. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs ret instruction pop rp instruction sp pc7 to pc0 higher register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 3 cpu architecture 64 users manual u15075ej1v0um00 3.2.2 general-purpose registers the general-purpose registers consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). general-purpose registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, or hl) or absolute names (r0 to r7 and rp0 to rp3). figure 3-18. general-purpose register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 3 cpu architecture users manual u15075ej1v0um00 65 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. the special function registers are allocated in the 256-byte area of ff00h to ffffh. special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions. the manipulatable bit units (1, 8, and 16) differ depending on the special function register type. the manipulatable bits can be specified as follows. ? 1-bit manipulation describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. when addressing an address, describe an even address. table 3-4 lists the special function registers. the meanings of the symbols in this table are as follows: ? symbol indicates the addresses of the implemented special function registers. the symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called sfrbit.h of the c compiler. therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. ?r/w indicates whether the special function register in question can be read or written. r/w: read/write r: read only w: write only ? bit manipulation unit indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated. ? after reset indicates the status of the special function register when the reset signal is input.
chapter 3 cpu architecture 66 users manual u15075ej1v0um00 table 3-4. special function register list (1/2) bit manipulation unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ?? - ff01h port 1 p1 ?? - ff02h port 2 p2 ?? - ff03h port 3 p3 ?? - ff05h port 5 p5 r/w ?? - ff06h port 6 p6 r ?? - ff07h port 7 p7 ?? - ff08h port 8 note 1 p8 ?? - ff09h port 9 note 1 p9 r/w ?? - 00h ff0ch 8-bit compare register 60 cr60 -? ff0dh 8-bit compare register 50 cr50 cr6 note 2 w -? ? notes 3, 4 undefined ff0eh 8-bit timer counter 60 tm60 -? ff0fh 8-bit timer counter 50 tm50 tm6 note 2 r -? ? notes 3, 4 00h transmit shift register 20 txs20 w -? - ffh ff10h receive buffer register 20 rxb20 sio20 r -? - undefined ff14h ff15h a/d conversion result register 0 adcr0 note 5 r -? ? notes 3 0000h ff16h ff17h 16-bit compare register 90 cr90 note 2 w -- ? notes 3, 4 ffffh ff18h ff19h 16-bit timer counter 90 tm90 note 2 -- ? notes 3, 4 0000h ff1ah 16-bit capture register 90 ff1bh tcp90 note 2 r -- ? note 3 undefined ff20h port mode register 0 pm0 ?? - ff21h port mode register 1 pm1 ?? - ff22h port mode register 2 pm2 ?? - ff23h port mode register 3 pm3 ?? - ff25h port mode register 5 pm5 r/w ?? - ffh notes 1. m pd789426 and 789436 subseries only. 2. name of sfr dedicated for 16-bit access. 3. only in short direct addressing, 16-bit access is possible. 4. these are 16-bit access dedicated registers, however, 8-bit access is possible. when performing 8-bit access, access using direct addressing. 5. when used as an 8-bit a/d converter ( m pd789426 and 789446 subseries), only 8-bit access is possible. in this case, the address is ff15h. when used as a 10-bit a/d converter ( m pd789436 and 789456 subseries), only 16-bit access is possible. when the m pd78f9436, a flash memory version of the m pd789425 or m pd789426, is used, this register can be accessed in 8-bit units. however, only an object file assembled with the m pd789425 or m pd789426 can be used. the same is also true for the m pd78f9456, a flash memory version of the m pd789445 or m pd789446: this register can be accessed in 8-bit units, but only an object file assembled with the m pd789445 or m pd789446 can be used.
chapter 3 cpu architecture users manual u15075ej1v0um00 67 table 3-4. special function register list (2/2) bit manipulation unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff27h port mode register 7 pm7 ?? - ff28h port mode register 8 note pm8 ?? - ff29h port mode register 9 note pm9 ?? - ffh ff32h pull-up resistor option register b2 pub2 ?? - ff33h pull-up resistor option register b3 pub3 ?? - ff37h pull-up resistor option register b7 pub7 ?? - ff38h pull-up resistor option register b8 note pub8 ?? - ff39h pull-up resistor option register b9 note pub9 ?? - ff42h watchdog timer clock select register wdcs -? - ff48h 16-bit timer mode control register 90 tmc90 ?? - ff49h buzzer output control register 90 bzc90 ?? - ff4ah watch timer mode control register wtm r/w ?? - 00h ff4ch 8-bit compare register h60 crh60 w -? - undefined ff4dh 8-bit timer mode control register 50 tmc50 ?? - ff4eh 8-bit timer mode control register 60 tmc60 r/w ?? - ff4fh carrier generator output control register 60 tca60 w ?? - ff70h asynchronous serial interface mode register 20 asim20 r/w ?? - ff71h asynchronous serial interface status register 20 asis20 r ?? - ff72h serial operation mode register 20 csim20 ?? - ff73h baud rate generator control register 20 brgc20 -? - ff80h a/d converter mode register 0 adm0 ?? - ff84h analog input channel specification register 0 ads0 ?? - ffb0h lcd display mode register 0 lcdm0 ?? - ffb2h lcd clock control register 0 lcdc0 ?? - ffb3h lcd voltage amplification control register 0 lcdva0 ?? - ffe0h interrupt request flag register 0 if0 ?? - ffe1h interrupt request flag register 1 if1 ?? - 00h ffe4h interrupt mask flag register 0 mk0 ?? - ffe5h interrupt mask flag register 1 mk1 ?? - ffh ffech external interrupt mode register 0 intm0 -? - ffedh external interrupt mode register 1 intm1 -? - fff0h suboscillation mode register sckm ?? - fff2h subclock control register css ?? - fff5h key return mode register 00 krm00 ?? - fff7h pull-up resistor option register 0 pu0 ?? - fff9h watchdog timer mode register wdtm ?? - 00h fffah oscillation stabilization time select register osts -? - 04h fffbh processor clock control register pcc r/w ?? - 02h note m pd789426 and 789436 subseries only.
chapter 3 cpu architecture 68 users manual u15075ej1v0um00 3.3 instruction address addressing an instruction address is determined by the program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of each instruction, refer to 78k/0s series instructions users manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (C128 to +127) and bit 7 becomes a sign bit. this means that information is relatively branched to a location between C128 and +127, from the start address of the next instruction when relative addressing is used. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 a jdisp8 when s = 0, a indicates all bits 0. ... pc is the start address of the next instruction of a br instruction. when s = 1, a indicates all bits 1.
chapter 3 cpu architecture users manual u15075ej1v0um00 69 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 instruction is executed. call !addr16 and br !addr16 instructions can be branched to any location in the memory space. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 3 cpu architecture 70 users manual u15075ej1v0um00 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. the instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4? instruction code 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture users manual u15075ej1v0um00 71 3.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated with immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 00101001op code 00000000 11111110 00h feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory ? ? ?
chapter 3 cpu architecture 72 users manual u15075ej1v0um00 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the whole sfr area. ports that are frequently accessed in a program and the compare register of the timer/event counter are mapped in this area, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 11110101 10010000 01010000 op code 90h (saddr-offset) 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset a when 8-bit immediate data is 20h to ffh, a = 0. when 8-bit immediate data is 00h to 1fh, a = 1.
chapter 3 cpu architecture users manual u15075ej1v0um00 73 3.4.3 special function register (sfr) addressing [function] the memory-mapped special function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 256-byte space ff00h to ffffh. however, the sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 11100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture 74 users manual u15075ej1v0um00 3.4.4 register addressing [function] in the register addressing mode, general-purpose registers are accessed as operands. the general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 10001000 register specification code incw de; when selecting the de register pair for rp instruction code 00001010 00100101 register specification code
chapter 3 cpu architecture users manual u15075ej1v0um00 75 3.4.5 register indirect addressing [function] in the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. the register pair to be accessed is specified by the register pair specification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description - [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 00101011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de addressed memory contents are transferred. memory address specified with register pair de.
chapter 3 cpu architecture 76 users manual u15075ej1v0um00 3.4.6 based addressing [function] 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description - [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 00101101 00010000 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. only the internal high-speed ram area can be addressed using stack addressing. [description example] in the case of push de instruction code 10101010
users manual u15075ej1v0um00 77 chapter 4 port functions 4.1 port functions the m pd789426, 789436, 789446, and 789456 subseries provide the ports shown in figures 4-1 and 4-2, enabling various methods of control. numerous other functions are provided that can be used in addition to the digital i/o port functions. for more information on these additional functions, see chapter 2 pin functions . figure 4-1. port types ( m m m m pd789426, 789436 subseries) p30 p33 p60 p00 p03 p10 p11 port 1 port 2 port 3 port 5 p20 p26 p65 port 0 port 6 p70 p72 port 8 port 7 p80 p81 p90 p97 port 9 p50 p53
chapter 4 port functions 78 users manual u15075ej1v0um00 figure 4-2. port types ( m m m m pd789446, 789456 subseries) p30 p33 p60 p00 p03 p10 p11 port 1 port 2 port 3 p20 p26 p65 port 0 p70 p72 port 7 port 6 p50 p53 port 5
chapter 4 port functions users manual u15075ej1v0um00 79 table 4-1. port functions (1/2) pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0) or key return mode register 00 (krm00). input kr0 to kr3 p10, p11 i/o port 1. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). input - p20 - p21 bzo90 p22 ss20 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b2 (pub2). input to90 p30 intp0/cpt90 p31 intp1/to50/tmi60 p32 intp2/to60 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b3 (pub3). input intp3/to61 p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by a mask option. input - p60 to p65 input port 6. 6-bit input port. input ani0 to ani5 p70 to p72 i/o port 7. 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b7 (pub7). input -
chapter 4 port functions 80 users manual u15075ej1v0um00 table 4-1. port functions (2/2) pin name i/o function after reset alternate function p80, p81 note i/o port 8. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b8 (pub8). input - p90 to p97 note i/o port 9. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b9 (pub9). input - note m pd789426, 789436 subseries only 4.2 port configuration ports have the following hardware configuration. table 4-2. configuration of port item configuration control registers port mode register (pmm: m = 0 to 3, 5, 7 to 9) pull-up resistor option register (pu0, pub2, pub3, pub7 to pub9) m pd789426, 789436 subseries total: 40 (cmos i/o: 30, cmos input: 6, n-ch open-drain i/o: 4) ports m pd789446, 789456 subseries total: 30 (cmos i/o: 20, cmos input: 6, n-ch open-drain i/o: 4) m pd789426, 789436 subseries total: 34 (software control: 30, mask option specification: 4) pull-up resistors m pd789446, 789456 subseries total: 24 (software control: 20, mask option specification: 4)
chapter 4 port functions users manual u15075ej1v0um00 81 4.2.1 port 0 this is a 4-bit i/o port with an output latch. port 0 can be specified in the input or output mode in 1-bit units by using the port mode register 0 (pm0). when the p00 to p03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (pu0). port 0 is set in the input mode when the reset signal is input. figure 4-3 shows a block diagram of port 0. figure 4-3. block diagram of p00 to p03 wr krm00 v dd p00/kr0 to p03/kr3 wr puo rd wr port w rpm pu00 pm00 to pm03 krm000 p-ch internal bus selector output latch (p00 to p03) alternate function krm00: key return mode register 00 pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions 82 users manual u15075ej1v0um00 4.2.2 port 1 this is a 2-bit i/o port with an output latch. port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (pm1). when using the p10 and p11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (pu0). this port is set in the input mode when the reset signal is input. figure 4-4 shows a block diagram of port 1. figure 4-4. block diagram of p10 and p11 pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal wr pu0 rd wr port wr pm pu01 pm10, pm11 v dd p-ch p10, p11 internal bus selector output latch (p10, p11)
chapter 4 port functions users manual u15075ej1v0um00 83 4.2.3 port 2 this is a 7-bit i/o port with an output latch. port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (pm2). when using the p20 to p26 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b2 (pub2). the port is also used as the serial interface i/o, buzzer output, and timer output. this port is set in the input mode when the reset signal is input. figures 4-5 to 4-10 show block diagrams of port 2. caution when using the pins of port 2 as the serial interface, the i/o or output latch must be set according to the function to be used. for how to set the latches, see figure 12-2 settings of serial interface 20 operating mode. figure 4-5. block diagram of p20 wr pub2 rd wr port wr pm pub20 output latch (p20) pm20 v dd p-ch p20 selector internal bus pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions 84 users manual u15075ej1v0um00 figure 4-6. block diagram of p21 and p26 internal bus v dd p-ch p21/bzo90, p26/to90 wr pub2 rd wr port wr pm pub21, pub26 output latch (p21, p26) pm21, pm26 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions users manual u15075ej1v0um00 85 figure 4-7. block diagram of p22 internal bus v dd p-ch p22/ss20 wr pub2 rd wr port wr pm pub22 alternate function output latch (p22) pm22 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions 86 users manual u15075ej1v0um00 figure 4-8. block diagram of p23 internal bus v dd p-ch p23/asck20/ sck20 wr pub2 rd wr port wr pm pub23 alternate function output latch (p23) pm23 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions users manual u15075ej1v0um00 87 figure 4-9. block diagram of p24 pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal internal bus v dd p24/so20/txd20 wr pub2 rd wr port wr pm pub24 alternate function output latch (p24) pm24 selector p-ch ss20 output
chapter 4 port functions 88 users manual u15075ej1v0um00 figure 4-10. block diagram of p25 p25/si20/ rxd20 wr pub2 rd wr port wr pm pub25 alternate function output latch (p25) pm25 v dd p-ch internal bus selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions users manual u15075ej1v0um00 89 4.2.4 port 3 this is a 4-bit i/o port with an output latch. port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (pm3). when using the p30 to p33 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b3 (pub3). this port is also used as an external interrupt input, capture input, and timer i/o. this port is set in the input mode when the reset signal is input. figures 4-11 and 4-12 show block diagrams of port 3. figure 4-11. block diagram of p30 p30/intp0/cpt90 wr pub3 rd wr port wr pm pub30 pm30 v dd p-ch internal bus alternate function selector output latch (p30) pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 4 port functions 90 users manual u15075ej1v0um00 figure 4-12. block diagram of p31 to p33 pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal p31/intp1/to50/ tmi60, p32/intp2/to60, p33/intp3/to61 wr pub3 rd wr port wr pm pub31 to pub33 pm31 to pm33 v dd p-ch internal bus alternate function selector output latch (p31 to p33) alternate function
chapter 4 port functions users manual u15075ej1v0um00 91 4.2.5 port 5 this is a 4-bit n-ch open-drain i/o port with an output latch. port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, use of an on-chip pull-up resistor can be specified by a mask option. this port is set in the input mode when the reset signal is input. figure 4-13 shows a block diagram of port 5. figure 4-13. block diagram of p50 to p53 internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd mask option resistor mask rom version only. for flash memory version, a pull-up resistor is not incorporated. pm: port mode register rd: port 5 read signal wr: port 5 write signal
chapter 4 port functions 92 users manual u15075ej1v0um00 4.2.6 port 6 this is an 8-bit input-only port. this port is also used as the analog input of an a/d converter. figure 4-14 shows a block diagram of port 6. figure 4-14. block diagram of port 6 v ref rd a/d converter p60/ani0 to p65/ani5 + - internal bus
chapter 4 port functions users manual u15075ej1v0um00 93 4.2.7 port 7 this is a 3-bit i/o port with an output latch. port 7 can be specified in the input or output mode in 1-bit units by using port mode register 7 (pm7). when using the p70 to p72 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b7 (pub7). this port is set in the input mode when the reset signal is input. figure 4-15 shows a block diagram of port 7. figure 4-15. block diagram of p70 to p72 wr pub7 rd wr port wr pm pub70 to pub72 output latch (p70 to p72) pm70 to pm72 v dd p-ch p70 to p72 internal bus selector pub7: pull-up resistor option register b7 pm: port mode register rd: port 7 read signal wr: port 7 write signal
chapter 4 port functions 94 users manual u15075ej1v0um00 4.2.8 port 8 ( m m m m pd789426, 789436 subseries only) this is a 2-bit i/o port with an output latch. port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (pm8). when using pins p80 and p81 as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b8 (pub8). this port is set in the input mode when the reset signal is input. figure 4-16 shows a block diagram of port 8. figure 4-16. block diagram of p80 and p81 pub8: pull-up resistor option register b8 pm: port mode register rd: port 8 read signal wr: port 8 write signal wr pub8 rd wr port wr pm pub80, pub81 output latch (p80, p81) pm80, pm81 v dd p-ch p80, p81 internal bus selector
chapter 4 port functions users manual u15075ej1v0um00 95 4.2.9 port 9 ( m m m m pd789426, 789436 subseries only) this is an 8-bit i/o port with an output latch. port 9 can be specified in the input or output mode in 1-bit units by using port mode register 9 (pm9). when using the pins of this port as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b9 (pub9). this port is set in the input mode when the reset signal is input. figure 4-17 shows a block diagram of port 9. figure 4-17. block diagram of p90 to p97 wr pub9 rd wr port wr pm pub90 to pub97 output latch (p90 to p97) pm90 to pm97 v dd p-ch p90 to p97 internal bus selector pub9: pull-up resistor option register b9 pm: port mode register rd: port 9 read signal wr: port 9 write signal
chapter 4 port functions 96 users manual u15075ej1v0um00 4.3 registers controlling port function the ports are controlled by the following two types of registers. port mode registers (pm0 to pm3, pm5, pm7 to pm9) pull-up resistor option registers (pu0, pub2, pub3, pub7 to pub9) (1) port mode registers (pm0 to pm3, pm5, pm7 to pm9) these registers are used to set port input/output in 1-bit units. the port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 4-3. caution as port 3 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be preset to 1.
chapter 4 port functions users manual u15075ej1v0um00 97 figure 4-18. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 1 1 1 1 1 1 1 1 1 1 1 1 pm03 pm13 pm53 pm02 pm12 pm52 pm01 pm11 pm51 pm00 pm10 pm50 pm0 pm1 pm5 7 symbol address after reset 6543210 r/w ff20h ff21h ff25h ffh ffh ffh r/w r/w r/w 1 1 1 1 1 pm72 pm71 pm70 pm7 ff27h ffh r/w 1 1 1 1 1 1 pm81 pm80 pm8 note ff28h ffh r/w pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9 note ff29h ffh r/w 1 1 pm26 1 pm25 1 pm24 1 pm23 pm33 pm22 pm32 pm21 pm31 pm20 pm30 pm2 pm3 ff22h ff23h ffh ffh r/w r/w pmn pin input/output mode selection (m = 0 to 3, 5, 7 to 9, n = 0 to 7) note incorporated only in the m pd789426 and 789436 subseries.
chapter 4 port functions 98 users manual u15075ej1v0um00 table 4-3. port mode register and output latch settings when using alternate functions alternate function pin name name i/o pmxx pxx p00 to p03 kr0 to kr3 input 1 x p26 to90 output 0 0 intp0 input 1 x p30 cpt90 input 1 x intp1 input 1 x to50 output 0 0 p31 tmi60 input 1 x intp2 input 1 x p32 to60 output 0 0 intp3 input 1 x p33 to61 output 0 0 p60 to p65 ani0 to ani5 input 1 x caution when port 2 is used as a serial interface pin, the i/o latch or output latch must be set according to its function. for the setting method, see table 12-2 settings of serial interface 20 operating mode. remark x: dont care pmxx: port mode register pxx: port output latch (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (pu0) sets whether on-chip pull-up registers are used on ports 0 and 1 or not. on the port specified to use an on-chip pull-up resistor by pu0, the pull-up resistor can be internally used only for the bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pu0. this also applies to cases when the pins are used for alternate functions. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pu0 to 00h. figure 4-19. format of pull-up resistor option register 0 pm on-chip pull-up resistor selection (m = 0, 1) 000000 pu01 pu00 pu0 address after reset r/w fff7h 00h r/w 765432<1><0> pu0m 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol caution bits 2 to 7 must be set to 0.
chapter 4 port functions users manual u15075ej1v0um00 99 (3) pull-up resistor option register b2 (pub2) pull-up resistor option register b2 (pub2) sets whether on-chip pull-up resistors on p20 to p26 are used or not. on the port specified to use an on-chip pull-up resistor by pub2, the pull-up resistor can be internally used only for the bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pub2. this also applies to cases when the pins are used for alternate functions. pub2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub2 to 00h. figure 4-20. format of pull-up resistor option register b2 p2n on-chip pull-up resistor selection (n = 0 to 6) 0 pub26 pub25 pub24 pub23 pub22 pub21 pub20 pub2 address after reset r/w ff32h 00h r/w 7 <6> <5> <4> <3> <2> <1> <0> pub2n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol (4) pull-up resistor option register b3 (pub3) pull-up resistor option register b3 (pub3) sets whether on-chip pull-up resistors on p30 to p33 are used or not. on the port specified to use an on-chip pull-up resistor by pub3, the pull-up resistor can be internally used only for the bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pub3. this also applies to cases when the pins are used for alternate functions. pub3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub3 to 00h. figure 4-21. format of pull-up resistor option register b3 p3n on-chip pull-up resistor selection (n = 0 to 3) 00 0 0 pub33 pub32 pub31 pub30 pub3 address after reset r/w ff33h 00h r/w 7654<3><2><1><0> pub3n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol
chapter 4 port functions 100 users manual u15075ej1v0um00 (5) pull-up resistor option register b7 (pub7) pull-up resistor option register b7 (pub7) sets whether on-chip pull-up resistors on p70 to p72 are used or not. on the port specified to use an on-chip pull-up resistor by pub7, the pull-up resistor can be internally used only for bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pub7. this also applies to when the pins are used for alternate function. pub7 is set with a 1-bit or 8-bit memory manipulation instructions. reset input sets pub7 to 00h. figure 4-22. format of pull-up resistor option register b7 p7n on-chip pull-up resistor selection (n = 0 to 2) 00 0 0 0 pub72 pub71 pub70 pub7 address after reset r/w ff37h 00h r/w 76543<2><1><0> pub7n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol (6) pull-up resistor option register b8 (pub8) note pull-up resistor option register b8 (pub8) sets whether on-chip pull-up resistors on p80 and p81 are used or not. on the port specified to use an on-chip pull-up resistor by pub8, the pull-up resistor can be internally used only for bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pub8. this also applies to when the pins are used for alternate functions. pub8 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub8 to 00h. note incorporated only in the m pd789426 and 789436 subseries. figure 4-23. format of pull-up resistor option register b8 p8n on-chip pull-up resistor selection (n = 0, 1) 000000 pub81 pub80 pub8 address after reset r/w ff38h 00h r/w 765432<1><0> pub8n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol
chapter 4 port functions users manual u15075ej1v0um00 101 (7) pull-up resistor option register b9 (pub9) note pull-up resistor option register b9 (pub9) sets whether on-chip pull-up resistors on p90 to p97 are used or not. on the port specified to use an on-chip pull-up resistor by pub9, the pull-up resistor can be internally used only for bits set in the input mode. no on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of pub9. this also applies to when the pins are used for alternate function. pub9 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub9 to 00h. note incorporated only in the m pd789426 and 789436 subseries. figure 4-24. format of pull-up resistor option register b9 p9n on-chip pull-up resistor selection (n = 0 to 7) pub97 pub96 pub95 pub94 pub93 pub92 pub91 pub90 pub9 address after reset r/w ff39h 00h r/w <7> <6> <5> <4> <3> <2> <1> <0> pub9n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol
chapter 4 port functions 102 users manual u15075ej1v0um00 4.4 port function operation the operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port by using a transfer instruction. the contents of the output latch can be output from the pins of the port. data once written to the output latch is retained until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a transfer instruction. however, the status of the port pin is not changed because the output buffer is off. data once written to the output latch is retained until new data is written to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the status of an output latch can be read by using a transfer instruction. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the result of the operation is written to the output latch. the contents of the output latch are output from the port pins. data once written to the output latch is retained until new data is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.
users manual u15075ej1v0um00 103 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. main system clock oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by the suboscillation mode register (sckm). 5.2 clock generator configuration the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
chapter 5 clock generator 104 users manual u15075ej1v0um00 figure 5-1. block diagram of clock generator f xt f x prescaler f x 2 2 f xt 2 1/2 prescaler 16-bit timer 90 8-bit timer 60 watch timer lcd controller/driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator x1 x2 xt1 xt2 main system clock oscillator
chapter 5 clock generator users manual u15075ej1v0um00 105 5.3 registers controlling clock generator the clock generator is controlled by the following registers. processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) (1) processor clock control register (pcc) pcc sets cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 02h. figure 5-2. format of processor clock control register control of main system clock oscillator operation mcc00000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w <7>6543210 mcc 0 1 operation enabled operation disabled cpu clock (f cpu ) selection note css0 0 0 1 1 pcc1 0 1 0 1 f x (0.2 s) f x /2 2 (0.8 s) f xt /2 (61 s) m m m note the cpu clock is selected according to a combination of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the subclock control register (css) (refer to 5.3 (3) subclock control register (css) ). cautions 1. bits 0 and 2 to 6 must be set to 0. 2. the mcc can be set only when the subsystem clock has been selected as the cpu clock. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 4. minimum instruction execution time: 2f cpu f cpu = 0.2 m s: 0.4 m s f cpu = 0.8 m s: 1.6 m s f cpu = 61 m s: 122 m s
chapter 5 clock generator 106 users manual u15075ej1v0um00 (2) suboscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sckm to 00h. figure 5-3. format of suboscillation mode register feedback resistor selection 000000frcscc sckm symbol address after reset r/w fff0h 00h r/w 76543210 frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled caution bits 2 to 7 must be set to 0.
chapter 5 clock generator users manual u15075ej1v0um00 107 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies the cpu clock operation status. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets css to 00h. figure 5-4. format of subclock control register cpu clock operation status 0 0 cls css0 0000 css address after reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the (divided) main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 (divided) output from the main system clock oscillator output from the subsystem clock oscillator symbol note note bit 5 is read only. caution bits 0 to 3, 6, and 7 must be set to 0.
chapter 5 clock generator 108 users manual u15075ej1v0um00 5.4 system clock oscillators 5.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-5 shows the external circuit of the main system clock oscillator. figure 5-5. external circuit of main system clock oscillator (a) crystal or ceramic oscillation (b) external clock crystal or ceramic resonator v ss x2 x1 external clock x1 x2
chapter 5 clock generator users manual u15075ej1v0um00 109 5.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the crystal resonator (32.768 khz typ.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 5-6 shows the external circuit of the subsystem clock oscillator. figure 5-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. when using the subsystem clock, particular care is required because the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption. figure 5-7 shows examples of incorrect resonator connection.
chapter 5 clock generator 110 users manual u15075ej1v0um00 figure 5-7. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0 to 3, 5) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to xt2 in series.
chapter 5 clock generator users manual u15075ej1v0um00 111 figure 5-7. examples of incorrect resonator connection (2/2) (e) signal is fetched (f) parallel and near signal lines of main system clock and subsystem clock v ss x1 x2 v ss x2 xt2 is wired parallel to x1. x1 xt2 xt1 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to xt2 in series. caution if the x1 wire is in parallel with the xt2 wire, crosstalk noise may occur between the x1 and xt2, resulting in a malfunction. to avoid this, do not lay the x1 and xt2 wires in parallel. 5.4.3 divider circuit the divider circuit divides the output of the main system clock oscillator (f x ) to generate various clocks. 5.4.4 when no subsystem clock is used if a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the xt1 and xt2 pins as follows: xt1: connect to v ss xt2: leave open in this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the suboscillation mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above.
chapter 5 clock generator 112 users manual u15075ej1v0um00 5.5 clock generator operation the clock generator generates the following clocks and controls the operation modes of the cpu, such as the standby mode. main system clock f x subsystem clock f xt cpu clock f cpu clock to peripheral hardware the operation and function of the clock generator is determined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclock control register (css), as follows. (a) the low-speed mode 2f cpu (1.6 m s: at 5.0 mhz operation) of the main system clock is selected when the reset signal is generated (pcc = 02h). while a low level is input to the reset pin, oscillation of the main system clock is stopped. (b) three types of cpu clocks f cpu (0.2 m s and 0.8 m s: main system clock (at 5.0 mhz operation), 61 m s: subsystem clock (at 32.768 khz operation)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt, can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (frc) of the sckm so that the on-chip feedback resistor cannot be used reduces current consumption in stop mode. in a system where a subsystem clock is used, setting sckm bit 0 to 1 can cause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsystem clock so that low current consumption operation is used (122 m s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possible to cause the main system clock to stop oscillating using bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock, but the subsystem clock pulse is only supplied to the 16-bit timer, 8-bit timer, watch timer, and lcd controller/driver. the 16-bit timer, 8-bit timer, watch timer, and lcd controller/driver can therefore keep running even during standby. the other hardware stops when the main system clock stops because it runs based on the main system clock (except for external input clock operations).
chapter 5 clock generator users manual u15075ej1v0um00 113 5.6 changing setting of system clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the setting of pcc has been changed, and the old clock is used for the duration of several instructions after that (see table 5-2 ). table 5-2. maximum time required for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 00011x 0 0 4 clocks 2f x /f xt clocks (306 clo cks) 1 2 clocks f x /2f xt clocks (76 clocks) 1 x 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execution time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. x: dont care
chapter 5 clock generator 114 users manual u15075ej1v0um00 5.6.2 switching between system clock and cpu clock the following figure illustrates how the cpu clock and system clock switch. figure 5-8. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f x f x f xt f x low-speed operation high-speed operation subsystem clock operation high-speed operation wait (6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on power application. the effect of resetting is released when the reset pin is later made high, and the main system clock starts oscillating. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts instruction execution at the slow speed of the main system clock (1.6 m s: at 5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that high-speed operation can be selected. <3> a drop of the v dd voltage is detected with an interrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status). <4> a recover of the v dd voltage is detected with an interrupt request signal. bit 7 (mcc) of pcc is set to 0, and then the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so that high-speed operation can be selected again. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
users manual u15075ej1v0um00 115 chapter 6 16-bit timer 6.1 16-bit timer functions the 16-bit timer has the following functions. timer interrupt timer output buzzer output count value capture (1) timer interrupt an interrupt is generated when a count value and compare value matches. (2) timer output timer output can be controlled when a count value and compare value matches. (3) buzzer output buzzer output can be controlled by software. (4) count value capture a count value of 16-bit timer counter 90 (tm90) is latched into a capture register synchronizing with the capture trigger and retained.
chapter 6 16-bit timer users manual u15075ej1v0um00 116 6.2 16-bit timer configuration the 16-bit timer includes the following hardware. table 6-1. 16-bit timer configuration item configuration timer counters 16 bits 1 (tm90) registers compare register: 16 bits 1 (cr90) capture register: 16 bits 1 (tcp90) timer outputs 1 (to90) control registers 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 2 (pm2)
chapter 6 16-bit timer users manual u15075ej1v0um00 117 internal bus internal bus 16-bit timer mode control register 90 (tmc90) tof90 cpt900 cpt901 16-bit capture register 90 (tcp90) 16-bit counter read buffer 16-bit timer counter 90 (tm90) 16-bit compare register 90 (cr90) f x /2 2 f x /2 6 f x /2 7 f xt ctp90/intp0 /ti81/p30 toc90 tcl901 tcl900 toe90 f/f tod90 p26 output latch p21 output latch pm26 pm21 to90/p26 inttm90 bzo90/p21 match ovf buzzer output control register (bzc90) 3 bcs902 bcs901 bcs900 bzoe90 edge detector synchronization circuit f x write controller write controller f x /2 cpu clock selector selector selector figure 6-1. block diagram of 16-bit timer
chapter 6 16-bit timer users manual u15075ej1v0um00 118 (1) 16-bit compare register 90 (cr90) a value specified in cr90 is compared with the count in 16-bit timer register 90 (tm90). if they match, an interrupt request (inttm90) is issued by cr90. cr90 is set with an 8-bit or 16-bit memory manipulation instruction. any value from 0000h to ffffh can be set. reset input sets cr90 to ffffh. cautions 1. cr90 is designed to be manipulated with a 16-bit memory manipulation instruction. however, it can also be manipulated with an 8-bit memory manipulation instruction. when an 8-bit memory manipulation instruction is used to set cr90, it must be accessed by direct addressing. 2. to overwrite cr90 during a count operation, it is necessary to disable interrupts in advance, using interrupt mask flag register 1 (mk1). it is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 90 (tmc90). if the value in cr90 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 90 (tm90) tm90 is used to count the number of pulses. the contents of tm90 are read with an 8-bit or 16-bit memory manipulation instruction. reset input sets tm90 to 0000h. cautions 1. the count becomes undefined when stop mode is deselected, because the count operation is performed before oscillation stabilizes. 2. tm90 is designed to be manipulated with a 16-bit memory manipulation instruction. however, it can also be manipulated with an 8-bit memory manipulation instruction. when an 8-bit memory instruction is used to manipulate tm90, it must be accessed by direct addressing. 3. when an 8-bit memory manipulation instruction is used to manipulate tm90, the lower and higher bytes must be read as a pair, in this order. (3) 16-bit capture register 90 (tcp90) tcp90 captures the contents of tm90. it is set with an 8-bit or 16-bit memory manipulation instruction. reset input makes tcp90 undefined. caution tcp90 is designed to be manipulated with a 16-bit memory manipulation instruction. however, it can also be manipulated with an 8-bit memory manipulation instruction. when an 8-bit memory manipulation instruction is used to manipulate tcp90, it must be accessed by direct addressing. (4) 16-bit counter read buffer 90 this buffer is used to latch and hold the count value for tm90.
chapter 6 16-bit timer users manual u15075ej1v0um00 119 6.3 registers controlling 16-bit timer the 16-bit timer is controlled by the following three registers. 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 2 (pm2) (1) 16-bit timer mode control register 90 (tmc90) 16-bit timer mode control register 90 (tmc90) controls the setting of a count clock, capture edge, etc. tmc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc90 to 00h.
chapter 6 16-bit timer users manual u15075ej1v0um00 120 figure 6-2. format of 16-bit timer mode control register 90 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 symbol address after reset r/w ff48h 00h r/w note 5 <6> 4321<0> <7> tof90 0 1 overflow flag control reset or cleared by software set when the 16-bit timer overflows cpt901 0 0 1 1 capture edge selection cpt900 0 1 0 1 capture operation disabled captured at the rising edge of the cpt90 pin captured at the falling edge of the cpt90 pin captured at both the rising and falling edges of the cpt90 pin toc90 0 1 timer output data inversion control inversion disabled inversion enabled tcl901 0 0 1 1 16-bit timer counter 90 count clock selection tcl900 0 1 0 1 toe90 0 1 16-bit timer counter 90 output control output disabled (port mode) output enabled tod90 0 1 timer output data timer output data is "0" timer output data is "1" f x /2 2 (1.25 mhz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f xt (32.768 khz) note bit 7 is read-only. caution disable interrupts in advance by using the interrupt mask flag register (mk1) to change the data of tcl901 and tcl900. also, prevent the timer output data from being inverted by setting toc90 to1. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer users manual u15075ej1v0um00 121 (2) buzzer output control register 90 (bzc90) this register selects a buzzer frequency based on fcl selected with the count clock select bits (tcl901 and tcl900), and controls the output of the square wave. bzc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets bzc90 to 00h. figure 6-3. format of buzzer output control register 90 bzoe90 buzzer port output control disables buzzer port output. enables buzzer port output. 0 1 0 0 0 0 bcs902 bcs901 bcs900 bzoe90 bzc90 symbol address after reset r/w ff49h 00h r/w 6 754 bcs902 bcs901 bcs900 buzzer frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 21 <0> fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt fcl/2 4 (78.1 khz) fcl/2 5 (39.1 khz) fcl/2 8 (4.88 khz) fcl/2 9 (2.44 khz) fcl/2 10 (1.22 khz) fcl/2 11 (610 hz) fcl/2 12 (305 hz) fcl/2 13 (153 hz) fcl/2 4 (4.88 khz) fcl/2 5 (2.44 khz) fcl/2 8 (305 hz) fcl/2 9 (153 hz) fcl/2 10 (76 hz) fcl/2 11 (38 hz) fcl/2 12 (19 hz) fcl/2 13 (10 hz) fcl/2 4 (2.44 khz) fcl/2 5 (1.22 khz) fcl/2 8 (153 hz) fcl/2 9 (76 hz) fcl/2 10 (38 hz) fcl/2 11 (19 hz) fcl/2 12 (10 hz) fcl/2 13 (5 hz) fcl/2 4 (2.05 khz) fcl/2 5 (1.02 khz) fcl/2 8 (128 hz) fcl/2 9 (64 hz) fcl/2 10 (32 hz) fcl/2 11 (16 hz) fcl/2 12 (8 hz) fcl/2 13 (4 hz) note note bits 4 to 7 must be set to 0. caution if the subclock is selected as the count clock (tcl901 = 1, tcl900 = 1: see figure 6-2 format of 16-bit timer mode control register 90), the subclock is not synchronized when buzzer port output is enabled. in this case, the capture function and tm90 read function are disabled. in addition, the count value of tm90 is undefined. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer users manual u15075ej1v0um00 122 (3) port mode register 2 (pm2) pm2 is used to set each bit of port 3 to input or output. when pin p26/ito90 is used for timer output, reset the output latch of p26 and pm26 to 0; when pin p21/bzo90 is used for buzzer output, reset the output latch of p26 and pm26 to 0. pm2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 6-4. format of port mode register 2 pm2n p2n pin i/o mode (n =1, 6) output mode (output buffer on) input mode (output buffer off) 0 1 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 symbol address after reset r/w ff22h ffh r/w 6 754 3 21 0
chapter 6 16-bit timer users manual u15075ej1v0um00 123 6.4 16-bit timer operation 6.4.1 operation as timer interrupt in the timer interrupt function, interrupts are repeatedly generated at the count value preset in 16-bit compare register 90 (cr90) based on the intervals of the value set in tcl901 and tcl900. to operate the 16-bit timer as a timer interrupt, the following settings are required. set count values in cr90 set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-5. figure 6-5. settings of 16-bit timer mode control register 90 for timer interrupt operation - 0/1 0/1 0/1 0/1 0 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) caution if both the cpt901 and cpt900 flags are set to 0, the capture operation is prohibited. when the count value of 16-bit timer counter 90 (tm90) matches the value set in cr90, counting of tm90 continues and an interrupt request signal (inttm90) is generated. table 6-2 shows interval time, and figure 6-6 shows timing of timer interrupt operation. caution when rewriting the value in cr90 during a count operation, be sure to execute the following processing. <1> set interrupt disabled (set tmmk90 (bit 4 of interrupt mask flag register 1 (mk1)) to 1). <2> disable inversion control of timer output data (set toc90 to 0) if the value in cr90 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. table 6-2. interval time of 16-bit timer tcl901 tcl900 count clock interval time 002 2 /f x (0.8 m s) 2 18 /f x (52.4 ms) 012 6 /f x (12.8 m s) 2 22 /f x (838.9 ms) 102 7 /f x (25.6 m s) 2 23 /f x (1.68 s) 111/f xt (30.5 m s) 2 16 /f xt (2.0 s) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer users manual u15075ej1v0um00 124 figure 6-6. timing of timer interrupt operation count clock tm90 count value cr90 inttm90 to90 tof90 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt acknowledgement interrupt acknowledgement overflow flag set t remark n = 0000h to ffffh
chapter 6 16-bit timer users manual u15075ej1v0um00 125 6.4.2 operation as timer output timer outputs are repeatedly generated at the count value preset in 16-bit compare register 90 (cr90) based on the intervals of the value set in tcl901 and tcl900. to operate the 16-bit timer as a timer output, the following settings are required. set p26 to output mode (pm26 = 0). reset output latch of p26 to 0. set the count value in cr90. set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-7. figure 6-7. settings of 16-bit timer mode control register 90 for timer output operation - 0/1 0/1 0/1 1 0 0/1 1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) inverse enable of timer output data to90 output enable caution if both the cpt901 flag and cpt900 flag are set to 0, the capture operation is prohibited. when the count value of 16-bit timer counter 90 (tm90) matches the value set in cr90, the output status of the to90/p26 pin is inverted. this enables timer output. at that time, tm90 counting continues and an interrupt request signal (inttm90) is generated. figure 6-8 shows the timing of timer output (see table 6-2 for the interval time of the 16-bit timer). figure 6-8. timer output timing count clock tm90 count value cr90 inttm90 to90 note tof90 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt acknowledgement interrupt acknowledgement overflow flag set t note the initial value of to90 becomes low level when output is enabled (toe90 = 1). remark n = 0000h to ffffh
chapter 6 16-bit timer users manual u15075ej1v0um00 126 6.4.3 capture operation the capture operation consists of latching the count value of 16-bit timer register 90 (tm90) into a capture register in synchronization with a capture trigger, and retaining the count value. set tmc90 as shown in figure 6-9 to allow the 16-bit timer to start the capture operation. figure 6-9. settings of 16-bit timer mode control register 90 for capture operation - 0/1 0/1 0/1 0/1 0 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 count clock selection capture edge selection (see table 6-3 ) 16-bit capture register 90 (tcp90) starts a capture operation after a cpt90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer register 90. the tcp90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. table 6-3 and figure 6-10 show the settings of the capture edge and the capture operation timing, respectively. table 6-3. settings of capture edge cpt901 cpt900 capture edge selection 0 0 capture operation prohibited 0 1 cpt90 pin rising edge 1 0 cpt90 pin falling edge 1 1 cpt90 pin both edges caution because tcp90 is rewritten when a capture trigger edge is detected during tcp90 read, disable the capture trigger edge detection during tcp90 read. figure 6-10. capture operation timing (both edges of cpt90 pin are specified) count clock tm90 count read buffer tcp90 cpt90 0000h 0000h 0001h 0001h undefined n n n m 1 m m m capture start capture start capture edge detection capture edge detection
chapter 6 16-bit timer users manual u15075ej1v0um00 127 6.4.4 16-bit timer counter 90 readout the count value of 16-bit timer counter 90 (tm90) is read out using a 16-bit manipulation instruction. tm90 readout is performed through a counter read buffer. the counter read buffer latches the tm90 count value, and the buffer operation is held pending at the cpu clock falling edge after the read signal of the tm90 lower byte rises, and the count value is retained. the retained counter read buffer value can be read out as the count value. cancellation of the pending state is performed at the cpu clock falling edge after the read signal of the tm90 higher byte falls. reset input sets tm90 to 0000h and tm90 starts freerunning. figure 6-11 shows the timing of 16-bit timer counter 90 readout. cautions 1. the count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. though tm90 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can also be used. when using an 8-bit transfer instruction, execute it by direct addressing. 3. when using an 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. if only the lower byte is read, the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read. figure 6-11. 16-bit timer counter 90 readout timing cpu clock count clock tm90 count read buffer tm90 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period
chapter 6 16-bit timer users manual u15075ej1v0um00 128 6.4.5 buzzer output operation the buzzer frequency is set using buzzer output control register 90 (bzc90) based on the count clock selected with tcl901 and tcl900 of tmc90 (source clock). a square wave of the set buzzer frequency is output. table 6-4 shows the buzzer frequency. set the 16-bit timer as follows to use it for buzzer output: set p21 to output mode (pm21 = 0). reset output latch of p21 to 0. set a count clock using tcl901 and tcl900. set bzc90 as shown in figure 6-12. figure 6-12. settings of buzzer output control register 90 for buzzer output operation 0 0 0 0 0/1 0/1 0/1 1 bcs902 bcs901 bcs900 bzoe90 bzc90 setting of buzzer frequency (see table 6-4 ) enables buzzer output table 6-4. buzzer frequency of 16-bit timer buzzer frequency bcs902 bcs901 bcs900 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt 000fcl/2 4 (78.1 khz) fcl/2 4 (4.88 khz) fcl/2 4 (2.44 khz) fcl/2 4 (2.05 khz) 001fcl/2 5 (39.1 khz) fcl/2 5 (2.44 khz) fcl/2 5 (1.22 khz) fcl/2 5 (1.02 khz) 010fcl/2 8 (4.88 khz) fcl/2 8 (305 hz) fcl/2 8 (153 hz) fcl/2 8 (128 hz) 011fcl/2 9 (2.44 khz) fcl/2 9 (153 hz) fcl/2 9 (76 hz) fcl/2 9 (64 hz) 100fcl/2 10 (1.22 khz) fcl/2 10 (76 hz) fcl/2 10 (38 hz) fcl/2 10 (32 hz) 101fcl/2 11 (610 hz) fcl/2 11 (38 hz) fcl/2 11 (19 hz) fcl/2 11 (16 hz) 110fcl/2 12 (305 hz) fcl/2 12 (19 hz) fcl/2 12 (10 hz) fcl/2 12 (8 hz) 111fcl/2 13 (153 hz) fcl/2 13 (10 hz) fcl/2 13 (5 hz) fcl/2 13 (4 hz) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer users manual u15075ej1v0um00 129 6.5 notes on using 16-bit timer usable functions differ according to the settings of the count clock selection, cpu clock operation, system clock oscillation status, and bzoe90 (bit 0 of buzzer output control register 90 (bzc90)). refer to the following table. system clock count clock cpu clock main system clock subsystem clock bzoe90 capture tm90 read buzzer output timer output timer interrupt oscillating ? ? note 1 note 2 ?? main stopped oscillating/stopped oscillating ? note 2 ?? f x /2 2 , f x /2 6 , f x /2 7 sub stopped oscillating 1/0 0 ???? oscillating 1 ??? oscillating stopped 1/0 0 oscillating 1 ??? main stopped (stop mode) stopped 1/0 0 ???? oscillating 1 ??? 0 f xt sub stopped oscillating 1 ??? notes 1. tm90 is enabled only when the cpu clock is in high-speed mode. 2. output is enabled when bzoe90 = 1. cautions 1. the capture function uses f x /2 for control (refer to figure 6-1 block diagram of 16-bit timer). therefore, the capture function cannot be used when the main system clock is stopped. 2. the read function of tm90 uses the cpu clock for control (refer to figure 6-1), and reads an undefined value when the cpu clock is slower than the count clock (values are not guaranteed). when reading tm90, set the count clock to the same speed as the cpu clock (when the cpu clock is the main system clock, high-speed mode is set), or select a clock slower than the cpu clock. 3. when the subsystem clock is selected as the count clock and bzoe90 is set to 0, the subsystem clock selected as the tm90 count clock is one that has been synchronized with the main system clock (refer to figure 6-1). therefore, when the main system clock oscillation is stopped, the timer operation is stopped because the clock supplied to the 16- bit timer is stopped (timer interrupt is not generated). moreover, when the subsystem clock is selected as the count clock and bzoe90 is set to 1, the capture and tm90 read values are not guaranteed because the subsystem clock is not synchronized. therefore, be sure to set bzoe90 to 0 when using the capture and tm90 read functions (when the subsystem clock is selected as the count clock, buzzer output, capture, and tm90 read functions cannot be used at the same time).
chapter 6 16-bit timer users manual u15075ej1v0um00 130 make the following settings when stopping the main system clock oscillation to support low current consumption and releasing the halt mode. count clock: subsystem clock cpu clock: subsystem clock main system clock: oscillation stopped bzoe90: 1 (buzzer output enabled) at this time, when the setting of p21, the buzzer output alternate function pin, is pm21 = 0, p21 = 0, a square wave of the buzzer frequency is output from p21. to avoid outputting the buzzer frequency, make either of the following settings. set p21 to input mode (pm21 = 1) if p21 cannot be set to input mode, set the port latch value of p21 to 1 (p21 = 1) (in this case, a high level is output from p21)
users manual u15075ej1v0um00 131 chapter 7 8-bit timer 7.1 8-bit timer functions an 8-bit timer (one channel, timer 50) and an 8-bit timer/event counter (one channel, timer 60) are incorporated in the m pd789426, 789436, 799446, 789456 subseries. the operation modes listed in the following table can be set via mode register settings. table 7-1. operation modes channel mode timer 50 timer 60 8-bit timer counter mode (discrete mode) available available 16-bit timer counter mode (cascade connection mode) available carrier generator mode available pwm output mode available (free-running mode) available (pulse generator mode) (1) 8-bit timer counter mode (discrete mode) the following functions can be used in this mode. interval timer with 8-bit resolution external event counter with 8-bit resolution (timer 40 only) square wave output with 8-bit resolution (2) 16-bit timer counter mode (cascade connection mode) operation as a 16-bit timer/event counter is enabled during cascade connection mode. the following functions can be used in this mode. interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution (3) carrier generator mode the carrier clock generated by timer 60 is output in cycles set by timer 50. (4) pwm output mode (a) timer 50: free-running mode the timer output status inverts repeatedly due to a match between tm50 and cr50 and tm50 overflow, and pulses of any duty ratio are output.
chapter 7 8-bit timer 132 users manual u15075ej1v0um00 (b) timer 60: pulse generator mode the timer output status inverts repeatedly due to the settings of tm60, cr60, and crh60, and pulses of any duty ratio are output (either p32/intp2/to60 or p33/intp3/to61 can be selected as the timer output pin using software). 7.2 8-bit timer configuration the 8-bit timer includes the following hardware. table 7-2. 8-bit timer configuration item configuration timer counters 8 bits 2 (tm50, tm60) registers compare registers: 8 bits 3 (cr50, cr60, crh60) timer outputs 3 (to50, to60, to61) control registers 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 60 (tmc60) carrier generator output control register 60 (tca60) port mode register 3 (pm3)
chapter 7 8-bit timer users manual u15075ej1v0um00 133 teg50 tcl500 tcl501 8-bit timer mode control register 50 (tmc50) decoder selector 8-bit compare register 50 (cr50) 8-bit timer counter 50 (tm50) from figure 7-2 (e) timer 60 match signal (in cascade connection mode) from figure 7-2 (d) count operation start signal (in cascade connection mode) inttm50 f x /2 3 f x /2 7 timer 60 interrupt request signal (from figure 7-2 (b)) carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) (from figure 7-2 (c)) cascade connection mode match internal bus ovf bit 7 of tm60 (from figure 7-2 (a)) toe50 p31 output latch pm31 to figure 7-2 (f) timer 50 match signal (in cascade connection mode) to50/tmi60/intp1/p31 tce50 tcl502 f x f xt tmd500 tmd501 s q in r q ck clear pwm mode to figure 7-2 (g) timer 50 match signal (in carrier generator mode) selector selector figure 7-1. block diagram of timer 50
chapter 7 8-bit timer 134 users manual u15075ej1v0um00 tce60 tcl602 tcl601 tcl600 tmd601 tmd600 toe60 8-bit timer mode control register 60 (tmc60) decoder 8-bit timer counter 60 (tm60) f/f clear 8-bit compare register 60 (cr60) selector output control ler note inttm60 match reset pwm mode cascade connection mode 8-bit compare register h60 (crh60) internal bus ovf f x f x /2 2 tmi60/to50 /intp1/p31 f tmi /2 f tmi /2 2 f tmi /2 3 to60/intp2/p32 f tmi rmc60 nrzb60 nrz60 carrier generator output control register 60 (tca60) to61/intp3/p33 prescaler selector count operation start signal to timer 50 (in cascade connection mode) to figure 7-1 (d) tm50 match signal (in cascade connection mode) tm60 timer counter match signal (in cascade connection mode) from figure 7-1 (f) to figure 7-1 (e) count clock input signal to tm50 to figure 7-1 (a) bit 7 of tm60 (in cascade connection mode) to figure 7-1 (c) carrier clock (during carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) to figure 7-1 (b) timer 60 interrupt request signal from figure 7-1 (g) timer counter match signal from timer 50 (in carrier generator mode) figure 7-2. block diagram of timer 60 note for details, see figure 7-3 .
chapter 7 8-bit timer users manual u15075ej1v0um00 135 figure 7-3. block diagram of output controller (timer 60) f/f pm32 p32 output latch to60/p32/ intp2 toe60 toe61 p33 output latch pm33 to61/p33/ intp3 timer 60 output signal (1) 8-bit compare register 50 (cr50) this 8-bit register is used to continually compare the value set to cr50 with the count value in 8-bit timer counter 50 (tm50) and to generate an interrupt request (inttm50) when a match occurs. cr50 is set with an 8-bit memory manipulation instruction. reset input makes cr50 undefined. cautions 1. if the cr50 is overwritten during timer operation in the pwm output mode (tmd501 = 1, tmd500 = 0), a high level may be output for 1 cycle immediately after. if this waveform poses a problem for the application, either <1> stop the timer when overwriting the cr50, or <2> overwrite the cr50 with the toe50 in a cleared status. 2. if the valid edge of the count clock is selected for both edges in the pwm output mode (teg50 = 1), do not set 00h, 01h, and ffh to the cr50. if the rising edge is selected (teg50 = 0), do not set 00h to cr50. (2) 8-bit compare register 60 (cr60) this 8-bit register is used to continually compare the value set to cr60 with the count value in 8-bit timer counter 60 (tm60) and to generate an interrupt request (inttm60) when a match occurs. when connected to tm50 via a cascade connection and used as a 16-bit timer/event counter, the interrupt request (inttm60) occurs only when matches occur simultaneously between cr50 and tm50 and between cr60 and tm60 (inttm50 does not occur). cr60 is set with an 8-bit memory manipulation instruction. reset input makes cr60 undefined. (3) 8-bit compare register h60 (crh60) in pwm output mode, the high-level width of timer output is set by writing a value to crh60. crh60 is set with an 8-bit memory manipulation instruction. reset input makes crh60 undefined.
chapter 7 8-bit timer 136 users manual u15075ej1v0um00 (4) 8-bit timer counters 50 and 60 (tm50 and tm60) these are 8-bit registers that are used to count the count pulse. tm50 and tm60 are read with an 8-bit memory manipulation instruction. reset input sets tm50 and tm60 to 00h. tm50 and tm60 are cleared to 00h under the following conditions. (a) discrete mode (i) tm50 after reset when tce50 (bit 7 of 8-bit timer mode control register 50 (tmc50)) is cleared to 0 when a match occurs between tm50 and cr50 when the tm50 count value overflows (ii) tm60 after reset when tce60 (bit 7 of 8-bit timer mode control register 60 (tmc60)) is cleared to 0 when a match occurs between tm60 and cr60 when the tm60 count value overflows (b) cascade connection mode (tm50 and tm60 are simultaneously cleared to 00h) after reset when the tce60 flag is cleared to 0 when matches occur simultaneously between tm50 and cr50 and between tm60 and cr60 when the tm50 and tm60 count values overflow simultaneously (c) carrier generator mode (i) tm50 after reset when the tce50 flag is cleared to 0 when a match occurs between tm50 and cr50 (ii) tm60 after reset when the tce60 flag is cleared to 0 when a match occurs between tm60 and cr60 when a match occurs between tm60 and crh60
chapter 7 8-bit timer users manual u15075ej1v0um00 137 (d) pwm output mode (i) tm50 after reset when the tce50 flag is cleared to 0 when a match occurs between tm50 and cr50 when the tm50 count value overflows (ii) tm60 reset when the tce60 flag is cleared to 0 when a match occurs between tm60 and crh60 when the tm60 count value overflows
chapter 7 8-bit timer 138 users manual u15075ej1v0um00 7.3 registers controlling 8-bit timer the 8-bit timer is controlled by the following four registers. 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 60 (tmc60) carrier generator output control register 60 (tca60) port mode register 3 (pm3) (1) 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 50 (tmc50) is used to control the timer 50 count clock setting and the operation mode setting. tmc50 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc50 to 00h.
chapter 7 8-bit timer users manual u15075ej1v0um00 139 figure 7-4. format of 8-bit timer mode control register 50 symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc50 tce50 teg50 tcl502 tcl501 tcl500 tmd501 tmd500 toe50 ff4dh 00h r/w tce50 control of tm50 count operation note 1 0 clears tm50 count value and stops operation 1 starts count operation teg50 valid edge selection for tm50 count clock 0 counts at the rising edge of the count clock 1 counts at both edges of the count clock note 2 tcl502 tcl501 tcl500 selection of timer 50 count clock 000f x (5.0 mhz) 001 f x /2 3 (625 khz) 010 f x /2 7 (39.1 khz) 011f xt (32.768 khz) 1 0 0 timer 60 match signal 1 0 1 carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) other than above setting prohibited tmd501 tmd500 tmd601 tmd600 selection of operation mode for timer 50 and timer 60 note 2 0 0 0 0 discrete mode (8-bit timer counter mode) 0 1 0 1 cascade connection mode (16-bit timer counter mode) 0 0 1 1 carrier generator mode 1 0 1 0 timer 50: pwm free-running mode timer 60: pwm pulse generator mode other than above setting prohibited toe50 control of timer output 0 output disabled 1 output enabled notes 1. since the count operation is controlled by tce40 (bit 7 of tmc40) in cascade connection mode, any setting for tce30 is ignored. 2. the selection of both edges is valid only in the pwm output mode. in 8-bit counter mode or cascade connection mode, counting is done using the rising edge even if teg50 is set to 1. 3. the operation mode selection is set to both the tmc30 register and tmc40 register.
chapter 7 8-bit timer 140 users manual u15075ej1v0um00 cautions 1. in cascade connection mode, the output signal of timer 60 is forcibly selected as the count clock. 2. when operating tmc50, be sure to perform settings in the following order. <1> stop tm50 count operation. <2> set the operation mode and the count clock. <3> start count operation. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) (2) 8-bit timer mode control register 60 (tmc60) 8-bit timer mode control register 60 (tmc60) is used to control the timer 60 count clock setting and the operation mode setting. tmc60 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc60 to 00h.
chapter 7 8-bit timer users manual u15075ej1v0um00 141 figure 7-5. format of 8-bit timer mode control register 60 symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc60 tce60 toe61 tcl602 tcl601 tcl600 tmd601 tmd600 toe60 ff4eh 00h r/w tce60 control of tm60 count operation note 1 0 clears tm60 count value and stops operation (the count value is also cleared for tm50 in cascade connection mode) 1 starts count operation (the count operation is also started for tm50 in cascade connection mode) tcl602 tcl601 tcl600 selection of timer 60 count clock 000f x (5.0 mhz) 001 f x /2 2 (1.25 mhz) 010f tmi (external input clock) 011f tmi /2 (external input clock) 100 f tmi /2 2 (external input clock) 101 f tmi /2 3 (external input clock) other than above setting prohibited tmd501 tmd500 tmd601 tmd600 selection of operation mode for timer 50 and timer 60 note 2 0 0 0 0 discrete mode (8-bit timer counter mode) 0 1 0 1 cascade connection mode (16-bit timer counter mode) 0 0 1 1 carrier generator mode 1 0 1 0 timer 50: pwm free-running mode timer 60: pwm pulse generator mode other than above setting prohibited toe61 toe60 control of timer output 0 0 output disabled 0 1 output enabled only for to60 1 0 output enabled only for to61 1 1 setting prohibited notes 1. since the count operation is controlled by tce60 (bit 7 of tmc60) in cascade connection mode, any setting for tce50 is ignored. 2. the operation mode selection is set to both the tmc50 register and tmc60 register. caution when operating the tmc60, be sure to perform settings in the following order. <1> stop the tm60 count operation. <2> set the operation mode and the count clock. <3> start count operation. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 7 8-bit timer 142 users manual u15075ej1v0um00 (3) carrier generator output control register 60 (tca60) this register is used to set the timer output data in carrier generator mode. tca60 is set with an 8-bit memory manipulation instruction. reset input sets tca60 to 00h. figure 7-6. format of carrier generator output control register 60 symbol76543<2><1><0>addressafter resetr/w tca60 0 0 0 0 0 rmc60 nrzb60 nrz60 ff4fh 00h w rmc60 control of remote control output 0 when nrzb60 = 1, a carrier pulse is output. when nrzb60 = 0, a low level is output. 1 when nrzb60 = 1, high-level signal is output. when nrzb60 = 0, a low level is output. nrzb60 this is the bit that stores the next data to be output to nrz60. when a match signal occurs (for a match with timer 50), the data is output to nrz60. input the required value to nrz60 by program beforehand. nrz60 no return zero data 0 outputs low-level signal (carrier clock is stopped) 1 outputs carrier pulse caution tca60 cannot be set with a 1-bit memory manipulation instruction. be sure to use an 8-bit memory manipulation instruction to set tca60. (4) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. when using the p31/to50/intp1/tmi60 pin as a timer output, set the pm31 and p31 output latch to 0. when using the p32/to60/intp2 pin as a timer output, set the pm32 and p32 output latch to 0. when using the p33/to61/intp3 pin as a timer output, set the pm33 and p33 output latch to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 7-7. format of port mode register 3 symbol76543210addressafter resetr/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm3n i/o mode of p3n pin (n = 0 to 3) 0 output mode (output buffer is on) 1 input mode (output buffer is off)
chapter 7 8-bit timer users manual u15075ej1v0um00 143 7.4 8-bit timer operation 7.4.1 operation as 8-bit timer counter timer 50 and timer 60 can be independently used as 8-bit timer counters. the following modes can be used for the 8-bit timer counter. interval timer with 8-bit resolution external event counter with 8-bit resolution (timer 60 only) square wave output with 8-bit resolution (1) operation as interval timer with 8-bit resolution the interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (crn0). to operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter n0 (tmn0) (tcen0 = 0). <2> disable timer output of ton0 (toen0 = 0). <3> set a count value in crn0. <4> set the operation mode of timer n0 to 8-bit timer counter mode (see figures 7-4 and 7-5). <5> set the count clock for timer n0 (see tables 7-3 to 7-6). <6> enable the operation of tmn0 (tcen0 = 1). when the count value of 8-bit timer counter n0 (tmn0) matches the value set in crn0, tmn0 is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmn0) is generated. tables 7-3 to 7-6 show interval time, and figures 7-8 to 7-13 show the timing of the interval timer operation. caution be sure to stop the timer operation before overwriting the count clock with different data. remark n = 5, 6
chapter 7 8-bit timer 144 users manual u15075ej1v0um00 table 7-3. interval time of timer 50 tcl502 tcl501 tcl500 minimum interval time maximum interval time resolution 0001/f x (0.2 m s) 2 8 /f x (51.2 m s) 1/f x (0.2 m s) 0012 3 /f x (1.6 m s) 2 11 /f x (409.6 m s) 2 3 /f x (1.6 m s) 0102 7 /f x (25.6 m s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 m s) 0111/f xt (30.5 m s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 m s) 1 0 0 input cycle of timer 60 match signal input cycle of timer 60 match signal 8 input cycle of timer 60 match signal 1 0 1 input cycle of timer 60 output i nput cycle of timer 60 output 8 input cycle of timer 60 remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency table 7-4. interval time of timer 60 tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0001/f x (0.2 m s) 2 8 /f x (51.2 m s) 1/f x (0.2 m s) 0012/f x (0.4 m s) 2 9 /f x (1.02 m s) 2/f x (0.4 m s) 010f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 011f tmi /2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 100f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 101f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency
chapter 7 8-bit timer users manual u15075ej1v0um00 145 figure 7-8. timing of interval timer operation with 8-bit resolution (basic operation) count stop count clock crn0 tcen0 inttmn0 tonm n t tmn0 n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement interval time interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 5, 6 nm = 50, 60, 61 figure 7-9. timing of interval timer operation with 8-bit resolution (when crn0 is set to 00h) count clock crn0 tcen0 inttmn0 tonm 00h tmn0 00h count start remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timer 146 users manual u15075ej1v0um00 figure 7-10. timing of interval timer operation with 8-bit resolution (when crn0 is set to ffh) count clock crn0 tcen0 inttmn0 tonm ffh tmn0 ffh 00h 01h 00h 01h 00h 01h 00h 01h ffh ffh ffh clear clear clear count start remark n = 5, 6 nm = 50, 60, 61 figure 7-11. timing of interval timer operation with 8-bit resolution (when crn0 changes from n to m (n < < < < m)) count clock crn0 tcen0 inttmn0 tonm tmn0 n 00h 00h n 00h 01h 00h 01h m nm n m clear clear clear count start interrupt acknowledgement interrupt acknowledgement crn0 overwritten remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timer users manual u15075ej1v0um00 147 figure 7-12. timing of interval timer operation with 8-bit resolution (when crn0 changes from n to m (n > > > > m)) count clock crn0 tcen0 inttmn0 tonm tmn0 00h 00h 00h n - 1 n mn m n m 00h ffh m h clear clear clear tmn0 overflows because m < n crn0 overwritten remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timer 148 users manual u15075ej1v0um00 figure 7-13. timing of interval timer operation with 8-bit resolution (when timer 60 match signal is selected for timer 50 count clock) timer 60 count clock cr60 tce60 inttm60 to60 tm60 n 00h m 00h 00h 01h m n m 00h m 00h 00h 01h y - 1 y 00h y 00h y input clock to timer 50 (timer 60 match signal) to50 inttm50 tce50 cr50 tm50 clear clear clear clear count start count start
chapter 7 8-bit timer users manual u15075ej1v0um00 149 (2) operation as external event counter with 8-bit resolution (timer 60 only) the external event counter counts the number of external clock pulses input to the tmi60/p31/intp1/to50 pin by using 8-bit timer counter 60 (tm60). to operate timer 60 as an external event counter, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 60 (tm60) (tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clock for timer 60 (see table 7-5). <5> set the operation mode of timer 60 to 8-bit timer counter mode (see figures 7-4 and 7-5). <6> set a count value in cr60. <7> enable the operation of tm60 (tce60 = 1). each time the valid edge is input, the value of tm60 is incremented. when the count value of tm60 matches the value set in cr60, tm60 is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttm60) is generated. figure 7-14 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count clock with different data.
chapter 7 8-bit timer 150 users manual u15075ej1v0um00 figure 7-14. timing of operation of external event counter with 8-bit resolution tmi60 pin input tm60 count value cr60 tce60 inttm60 00h 01h 02h 03h 04h 05h n - 1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 7 8-bit timer users manual u15075ej1v0um00 151 (3) operation as square-wave output with 8-bit resolution square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register n0 (crn0). to operate timer n0 for square-wave output, settings must be made in the following sequence. <1> when using timer 50, set p31 to output mode (pm31 = 0). when using timer 60, set p32 to output mode (pm32 = 0) or set p33 to output mode (pm33 = 0) (when to61 is selected as timer output). <2> set the output latches of p31, p32, and p33 to 0. <3> disable operation of timer counter n0 (tmn0) (tcen0 = 0). <4> set a count clock for timer n0 and enable output of ton0 (toen0 = 1) note . <5> set a count value in crn0. <6> enable the operation of tmn0 (tcen0 = 1). when the count value of tmn0 matches the value set in crn0, the ton0 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tmn0 is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmn0) is generated. the square-wave output is cleared to 0 by setting tcen0 to 0. tables 7-5 and 7-6 show the square-wave output range, and figure 7-15 shows the timing of square-wave output. note in the case of timer 60, either to60 or to61 can be selected as the timer output pin. if to61 is selected, set toe61 = 1. caution be sure to stop the timer operation before overwriting the count clock with different data. remark n = 5, 6 table 7-5. square-wave output range of timer 50 (during f x = 5.0 mhz operation) tcl502 tcl501 tcl500 minimum pulse width maximum pulse width resolution 0001/f x (0.2 m s) 2 8 /f x (51.2 m s) 1/f x (0.2 m s) 0012 3 /f x (1.6 m s) 2 11 /f x (409.6 m s) 2 3 /f x (1.6 m s) 0102 7 /f x (25.6 m s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 m s) 0111/f xt (30.5 m s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 m s) 1 0 0 input cycle of timer 60 match signal input cycle of timer 60 match signal 8 input cycle of timer 60 match signal 1 0 1 input cycle of timer 60 output i nput cycle of timer 60 output 8 input cycle of timer 60 remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 7 8-bit timer 152 users manual u15075ej1v0um00 table 7-6. square-wave output range of timer 60 (during f x = 5.0 mhz operation) tcl602 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0001/f x (0.2 m s) 2 8 /f x (51.2 m s) 1/f x (0.2 m s) 0012/f x (0.4 m s) 2 9 /f x (1.02 ms) 2/f x (0.4 m s) 010f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 011f tmi /2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 100f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 101f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency figure 7-15. timing of square-wave output with 8-bit resolution count clock crn0 tcen0 inttmn0 tonm note n tmn0 n 00h 01h n 00h 01h n 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement note the initial value of tonm is low level when output is enabled (toenm = 1). remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timer users manual u15075ej1v0um00 153 7.4.2 operation as 16-bit timer counter timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. in this case, 8-bit timer counter 50 (tm50) is the higher 8 bits and 8-bit timer counter 60 (tm60) is the lower 8 bits. 8-bit timer 60 controls reset and clear. the following modes can be used for the 16-bit timer counter. interval timer with 16-bit resolution external event counter with 16-bit resolution square-wave output with 16-bit resolution (1) operation as interval timer with 16-bit resolution the interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 50 (cr50) and 8-bit compare register 60 (cr60). to operate as an interval timer with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 50 (tm50) and 8-bit timer counter 60 (tm60) (tce50 = 0, tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set the count clock for timer 60 (see tables 7-5 and 7-6). <4> set the operation mode of timer 50 and 8-bit timer 60 to 16-bit timer counter mode (see figures 7-4 and 7-5). <5> set a count value in cr50 and cr60. <6> enable the operation of tm50 and tm60 (tce60 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). when the count values of tm50 and tm60 match the values set in cr50 and cr60 respectively, both tm50 and tm60 are simultaneously cleared to 00h and counting continues. at the same time, an interrupt request signal (inttm60) is generated (inttm50 is not generated). table 7-7 shows interval time, and figure 7-16 shows the timing of the interval timer operation. cautions 1. be sure to stop the timer operation before overwriting the count clock with different data. 2. in the 16-bit timer counter mode, to50 cannot be used. be sure to set toe50 = 0 to disable to50 output.
chapter 7 8-bit timer 154 users manual u15075ej1v0um00 table 7-7. interval time with 16-bit resolution (during f x = 5.0 mhz operation) tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0001/f x (0.2 m s) 2 16 /f x (13.1 ms) 1/f x (0.2 m s) 0012/f x (0.4 m s) 2 17 /f x (26.2 ms) 2/f x (0.4 m s) 010f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 011f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 100f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 101f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency
chapter 7 8-bit timer users manual u15075ej1v0um00 155 interval time count clock tm60 count value cr60 tce60 inttm60 to60 or to61 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x - 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x - 1 00h t not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement remark interval time = (256x + n + 1) t: x = 00h to ffh, n = 00h to ffh figure 7-16. timing of interval timer operation with 16-bit resolution
chapter 7 8-bit timer 156 users manual u15075ej1v0um00 (2) operation as external event counter with 16-bit resolution the external event counter counts the number of external clock pulses input to the tmi60/p31/intp1/to50 pin by tm50 and tm60. to operate as an external event counter with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clock for timer 60 (see tables 7-5 and 7-6). <5> set the operation mode of timer 50 and 8-bit timer 60 to 16-bit timer counter mode (see figures 7-4 and 7-5). <6> set a count value in cr50 and cr60. <7> enable the operation of tm50 and tm60 (tce60 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). each time the valid edge is input, the values of tm50 and tm60 are incremented. when the count values of tm50 and tm60 simultaneously match the values set in cr50 and cr60 respectively, both tm50 and tm60 are cleared to 00h and counting continues. at the same time, an interrupt request signal (inttm60) is generated (inttm50 is not generated). figure 7-17 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count clock with different data.
chapter 7 8-bit timer users manual u15075ej1v0um00 157 tmi60 pin input tm60 count value cr60 tce60 inttm60 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x - 1 00h x - 1 not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement remark x = 00h to ffh, n = 00h to ffh figure 7-17. timing of external event counter operation with 16-bit resolution
chapter 7 8-bit timer 158 users manual u15075ej1v0um00 (3) operation as square-wave output with 16-bit resolution square waves of any frequency can be output at an interval specified by the count value preset in cr50 and cr60. to operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable output of to50 and to60 (toe50 = 0, toe60 = 0). <3> set a count clock for timer 60. <4> select either to60 or to61 as the timer output pin. if to60 is selected: set p32 to the output mode (pm32 = 0), set the p32 output latch to 0, and set to60 to output enable (to60 = 1). (use of to50 is prohibited.) if to61 is selected: set p33 to the output mode (pm33 = 0), set the p33 output latch to 0, and set to61 to output enable (toe61 = 1). (use of to50 is prohibited.) <5> set count values in cr50 and cr60. <6> enable the operation of tm60 (tce60 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). when the count values of tm50 and tm60 simultaneously match the values set in cr50 and cr60 respectively, the to60 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tm50 and tm60 are cleared to 00h and counting continues. at the same time, an interrupt request signal (inttm60) is generated (inttm50 is not generated). the square-wave output is cleared to 0 by setting tce60 to 0. table 7-8 shows the square wave output range, and figure 7-18 shows timing of square wave output. cautions 1. be sure to stop the timer operation before overwriting the count clock with different data. 2. in the 16-bit timer counter mode, to50 cannot be used. be sure to set toe50 = 0 to disable to50 output. remark items in parentheses are for when the to61 pin is selected for timer output. table 7-8. square-wave output range with 16-bit resolution (during f x = 5.0 mhz operation) tcl602 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0001/f x (0.2 m s) 2 16 /f x (13.1 ms) 1/f x (0.2 m s) 0012/f x (0.4 m s) 2 17 /f x (26.2 ms) 2/f x (0.4 m s) 010f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 011f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 100f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 101f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency
chapter 7 8-bit timer users manual u15075ej1v0um00 159 count clock tm60 count value cr60 tce60 inttm60 to60 or to61 note ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x - 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x - 1 00h not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement figure 7-18. timing of square-wave output with 16-bit resolution note the initial value of to60 or to61 is low level when output is enabled. remark x = 00h to ffh, n = 00h to ffh
chapter 7 8-bit timer 160 users manual u15075ej1v0um00 7.4.3 operation as carrier generator an arbitrary carrier clock generated by tm60 can be output in the cycle set in tm50. to operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable timer output of to50 and to60 (toe50 = 0, toe60 = 0). <3> set count values in cr50, cr60, and crh60. <4> set the operation mode of timer 50 and timer 60 to carrier generator mode (see figures 7-4 and 7-5). <5> set the count clock for timer 50 and timer 60. <6> set remote control output to carrier pulse (rmc60 (bit 2 of carrier generator output control register 60 (tca60)) = 0). input the required value to nrzb60 (bit 1 of tca60) by program. input a value to nrz60 (bit 0 of tca60) before it is reloaded from nrzb60. <7> select either to60 or to61 as the timer output pin. if to60 is selected: set p32 to the output mode (pm32 = 0), set the p32 output latch to 0, and set toe60 to output enable (toe60 = 1). if to61 is selected: set p33 to the output mode (pm33 = 0), set the p33 output latch to 0, and set toe61 to output enable (toe60 = 1). <8> enable the operation of tm50 and tm60 (tce50 = 1, tce60 = 1). the operation of the carrier generator is as follows. <1> when the count value of tm60 matches the value set in cr60, an interrupt request signal (inttm60) is generated and output of timer 60 is inverted, which makes the compare register switch from cr60 to crh60. <2> after that, when the count value of tm60 matches the value set in crh60, an interrupt request signal (inttm60) is generated and output of timer 60 is inverted again, which makes the compare register switch from crh60 to cr60. <3> the carrier clock is generated by repeating <1> and <2> above. <4> when the count value of tm50 matches the value set in cr50, an interrupt request signal (inttm50) is generated. the rising edge of inttm50 is the data reload signal of nrzb60 and is transferred to nrz60. <5> when nrz60 is 1, a carrier clock is output from the to60 pin (or the to61 pin). cautions 1. tca60 cannot be set with a 1-bit memory manipulation instruction. be sure to use an 8-bit memory manipulation instruction. 2. when setting the carrier generator operation again after stopping it once, reset nrzb60 because the previous value is not retained. in this case also a 1-bit memory manipulation instruction cannot be used. be sure to use an 8-bit memory manipulation instruction. figures 7-19 to 7-21 show the operation timing of the carrier generator.
chapter 7 8-bit timer users manual u15075ej1v0um00 161 figure 7-19. timing of carrier generator operation (when cr60 = n, crh60 = m (m > > > > n)) count clock tm60 count value cr60 tce60 inttm60 m 00h n 00h 01h n crh60 m n 00h carrier clock n 00h 00h n m 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 or to61 carrier clock clear clear clear clear count start
chapter 7 8-bit timer 162 users manual u15075ej1v0um00 figure 7-20. timing of carrier generator operation (when cr60 = n, crh60 = m (m < < < < n), phases of carrier clock and nrz60 are asynchronous) count clock tm60 count value cr60 tce60 inttm60 n 00h n crh60 m carrier clock n 00h 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 or to61 carrier clock m 00h m m 00h m 00h clear clear clear clear count start
chapter 7 8-bit timer users manual u15075ej1v0um00 163 figure 7-21. timing of carrier generator operation (when cr60 = crh60 = n) count clock tm60 count value cr60 tce60 inttm60 n 00h 00h 00h n crh60 n n carrier clock 00h 00h n n 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 or to61 carrier clock n n 00h clear clear clear clear clear count start
chapter 7 8-bit timer 164 users manual u15075ej1v0um00 7.4.4. pwm free-running mode operation (timer 50) in the pwm free-running mode, to50 becomes high level when tm50 overflows, and to50 becomes low level when cr50 and tm50 match. it is thus possible to output a pulse with any duty ratio. to operate timer 50 in the pwm free-running mode, setting must be made in the following sequence. <1> disable operation of tm50 (tce50 = 0). <2> disable timer output of to50 (toe50 = 0). <3> set a count value to cr50. <4> set the operation mode of timer 50 to the pwm free-running mode. (see figure 7-4.) <5> set the count clock for timer 50. <6> set p31 to the output mode (pm31 = 0) and the p31 output latch to 0 and enable timer output of to50 (toe50 = 1). <7> enable the operation of tm50 (tce50 = 1). the operation in the pwm free-running mode is as follows. <1> when the count value of tm50 matches the value set in cr50, an interrupt request signal (inttm50) is generated and a low level is output by the to50. the tm50 continues counting without being cleared. <2> to50 outputs a high level when the tm50 overflows. a pulse of any duty is output by repeating the above procedure. figures 7-22 to 7-25 show the operation timing in the pwm free-running mode.
chapter 7 8-bit timer users manual u15075ej1v0um00 165 figure 7-22. operation timing in pwm free-running mode (when rising edge is selected) count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh n ffh n overflow overflow count start caution when the rising edge is selected, do not set the cr50 to 00h. if the cr50 is set to 00h, pwm output may not be performed normally. figure 7-23. operation timing when overwriting cr50 (when rising edge is selected) (1/2) (1) when setting cr50 > > > > tm50 after overflow count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh m ffh 01h m overflow overflow overflow count start cr50 overwrite
chapter 7 8-bit timer 166 users manual u15075ej1v0um00 figure 7-23. operation timing when overwriting cr50 (when rising edge is selected) (2/2) (2) when setting cr50 < < < < tm50 after overflow count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh ffh 01h 01h 02h 01h overflow overflow overflow count start cr50 overwrite overflow occurs but no change takes place because to50 is high level. figure 7-24. operation timing in pwm free-running mode (when both edges are selected) (1/2) (1) cr50 = even number count clock cr50 tce50 inttm50 to50 2n tm50 2n 00h 00h 01h ffh ffh 2n 02h feh 01h 02h feh overflow overflow overflow count start
chapter 7 8-bit timer users manual u15075ej1v0um00 167 figure 7-24. operation timing in pwm free-running mode (when both edges are selected) (2/2) (2) when cr50 = odd number count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n + 1 00h 00h 01h ffh ffh 2n + 1 01h 01h 00h overflow overflow overflow count start caution when both edges are selected, do not set cr50 to 00h, 01h, and ffh. if the cr50 is set to these values, pwm output may not be performed normally. figure 7-25. operation timing in pwm free-running mode (when both edges are selected) (when cr50 is overwritten) count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n 00h 00h 00h 01h ffh ffh 01h 2n + 1 01h 02h feh 2n overflow overflow overflow count start cr50 overwrite
chapter 7 8-bit timer 168 users manual u15075ej1v0um00 7.4.5 operation as pwm output (timer 60) in the pwm pulse generator mode, a pulse of any duty ratio can be output by setting a low-level width using cr60 and a high-level width using crh60. to operate timer 60 in pwm output mode, settings must be made in the following sequence. <1> disable operation of tm60 (tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set count values in cr60 and crh60. <4> set the operation mode of timer 60 to the pwm pulse generator mode (see figure 7-5). <5> set the count clock for timer 60. <6> set p32 to the output mode (pm32 = 0) and the p32 output latch to 0 and enable timer output of to60 (toe60 = 1). <7> enable the operation of tm60 (tce60 = 1). the operation in the pwm output mode is as follows. <1> when the count value of tm60 matches the value set in cr60, an interrupt request signal (inttm60) is generated and output of timer 60 is inverted, which makes the compare register switch from cr60 to crh60. <2> a match between tm60 and cr60 clears the tm60 value to 00h and then counting starts again. <3> after that, when the count value of tm60 matches the value set in crh60, an interrupt request signal (inttm60) is generated and output of timer 60 is inverted again, which makes the compare register switch from crh60 to cr60. <4> a match between tm60 and crh60 clears the tm60 value to 00h and then counting starts again. a pulse of any duty ratio is output by repeating <1> to <4> above. figures 7-26 and 7-27 show the operation timing in the pwm output mode.
chapter 7 8-bit timer users manual u15075ej1v0um00 169 figure 7-26. pwm pulse generator mode timing (basic operation) count clock tm60 count value cr60 tce60 inttm60 00h n 00h 01h n crh60 m n to60 or to61 note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of to60 is low level when output is enabled (toe60 = 1). figure 7-27. pwm output mode timing (when cr60 and crh60 are overwritten) count clock tm60 count value cr60 tce60 inttm60 00h n 00h 01h n crh60 m n to60 or to61 note m x y 00h 00h x 00h x ym clear clear clear clear count start note the initial value of to60 is low level when output is enabled (toe60 = 1).
chapter 7 8-bit timer 170 users manual u15075ej1v0um00 7.5 notes on using 8-bit timer (1) error on starting timer an error of up to 1 clock is included in the time between the timer being started and a match signal being generated. this is because 8-bit timer counter n0 (tmn0) is started asynchronously to the count pulse. figure 7-28. start timing of 8-bit timer counter count pulse tmn0 count value 00h 01h 02h 03h 04h timer start remark n = 5, 6 (2) setting of 8-bit compare register n0 8-bit compare register n0 (crn0) can be set to 00h. therefore, one pulse can be counted when the 8-bit timer operates as an event counter. figure 7-29. timing of operation as external event counter (8-bit resolution) tmi60 input cr60 00h tm60 count value 00h 00h 00h 00h interrupt request flag
users manual u15075ej1v0um00 171 chapter 8 watch timer 8.1 watch timer functions the watch timer has the following functions. watch timer interval timer the watch and interval timers can be used at the same time. figure 8-1 is a block diagram of the watch timer. figure 8-1. block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector
chapter 8 watch timer users manual u15075ej1v0um00 172 (1) watch timer the 4.19 mhz main system clock or 32.768 khz subsystem clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clock is operating at 5.0 mhz, it cannot be used to generate a 0.5- second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interrupt request (intwti) at specified intervals. table 8-1. interval generated using the interval timer interval at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 2 4 1/f w 409.6 m s 489 m s 488 m s 2 5 1/f w 819.2 m s 978 m s 977 m s 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 8.2 watch timer configuration the watch timer includes the following hardware. table 8-2. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 8 watch timer users manual u15075ej1v0um00 173 8.3 watch timer control register the watch timer is controlled by the watch timer mode control register (wtm). ? watch timer mode control register (wtm) wtm selects a count clock for the watch timer and specifies whether to enable operation of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 8-2. format of watch timer mode control register watch timer count clock selection wtm7 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) wtm5 0 0 1 1 0 0 wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started watch timer operation wtm0 0 1 operation disabled (both prescaler and timer cleared) operation enabled other than above f x /2 7 f xt (39.1 khz) (32.768 khz) setting prohibited wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm 76 54 symbol address after reset r/w ff4ah 00h r/w 3210 0 1 m m remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f w = 32.768 khz.
chapter 8 watch timer users manual u15075ej1v0um00 174 8.4 watch timer operation 8.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used to enable the watch timer to operate at 0.5-second intervals. the watch timer is used to generate an interrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch timer mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. it is possible to start the watch timer only from zero seconds by clearing wtm1 to 0 when the interval timer and watch timer operate at the same time. in this case, however, an error of up to 2 9 1/f w seconds may occur in the overflow (intwt) after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0. 8.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value. the interval can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 8-3. interval time of interval timer wtm6 wtm5 wtm4 interval at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 0002 4 1/f w 409.6 m s 489 m s 488 m s 0012 5 1/f w 819.2 m s 978 m s 977 m s 0102 6 1/f w 1.64 ms 1.96 ms 1.95 ms 0112 7 1/f w 3.28 ms 3.91 ms 3.91 ms 1002 8 1/f w 6.55 ms 7.82 ms 7.81 ms 1012 9 1/f w 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency
chapter 8 watch timer users manual u15075ej1v0um00 175 figure 8-3. watch timer/interval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t caution when operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (wtm0) of the watch mode timer mode control register (wtm) to 1, the interval until the first interrupt request (intwt) is generated after the register is set does not exactly match the specification made with wtm3 (bit 3 of wtm). this is because there is a delay of one 9-bit pre- scaler output cycle until the 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. remarks 1. f w : watch timer clock frequency 2. the parenthesized values apply to operation at f w = 32.768 khz.
users manual u15075ej1v0um00 176 [memo]
users manual u15075ej1v0um00 177 chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions. watchdog timer interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect a program runaway. when a runaway is detected, a non-maskable interrupt or the reset signal can be generated. table 9-1. watchdog timer runaway detection time runaway detection time at f x = 5.0 mhz 2 11 1/f x 410 m s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at an arbitrary preset interval. table 9-2. interval time interval at f x = 5.0 mhz 2 11 1/f x 410 m s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency
chapter 9 watchdog timer users manual u15075ej1v0um00 178 9.2 watchdog timer configuration the watchdog timer includes the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) figure 9-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 3 7-bit counter tmif4 tmmk4 tcl22 tcl21 tcl20 watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) clear wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4
chapter 9 watchdog timer users manual u15075ej1v0um00 179 9.3 watchdog timer control registers the watchdog timer is controlled by the following two registers. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer count clock. wdcs is set with an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 9-2. format of watchdog timer clock select register wdcs2 0 0 1 1 wdcs1 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) wdcs0 0 0 0 0 setting prohibited other than above watchdog timer count clock selection 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x (410 s) (1.64 ms) (6.55 ms) (26.2 ms) interval m 0 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs 76 54 symbol address after reset r/w ff42h 00h r/w 3210 remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 9 watchdog timer users manual u15075ej1v0um00 180 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3. format of watchdog timer mode register run 0 1 watchdog timer operation selection note 1 stops counting. clears counter and starts counting. wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (generates a maskable interrupt upon overflow occurrence.) note 3 watchdog timer mode 1 (generates a non-maskable interrupt upon overflow occurrence.) watchdog timer mode 2 (starts reset operation upon overflow occurrence.) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 notes 1. once run has been set (1), it cannot be cleared (0) by software. therefore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set (1), they cannot be cleared (0) by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock select register (wdcs). 2. to set watchdog timer mode 1 or 2, set wdtm4 to 1 after confirming tmif4 (bit 0 of the interrupt request flag register 0 (if0)) is set to 0. when watchdog timer mode 1 or 2 is selected with tmif4 set to 1, a non-maskable interrupt is generated upon the completion of rewriting wdtm4.
chapter 9 watchdog timer users manual u15075ej1v0um00 181 9.4 watchdog timer operation 9.4.1 operation as watchdog timer the watchdog timer detects a program runaway when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (wdcs0 to wdcs2) of watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set runaway detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start counting. if run is not set to 1, and the runaway detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before executing the stop instruction. cautions 1. the actual runaway detection time may be up to 0.8% shorter than the set time. 2. when the subsystem clock is selected as the cpu clock, the watchdog timer count operation is stopped. even when the main system clock continues oscillating in this case, watchdog timer count operation is stopped. table 9-4. watchdog timer runaway detection time wdcs2 wdcs1 wdcs0 runaway detection time at f x = 5.0 mhz 0002 11 1/f x 410 m s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency
chapter 9 watchdog timer users manual u15075ej1v0um00 182 9.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. select a count clock (or interval) by setting bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). the watchdog timer starts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (wdtmk) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before executing the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless the reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 9-5. interval time of interval timer wdcs2 wdcs1 wdcs0 interval at f x = 5.0 mhz 0002 11 1/f x 410 m s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency
users manual u15075ej1v0um00 183 chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) 10.1 8-bit a/d converter functions the 8-bit a/d converter is an 8-bit resolution converter used to convert analog inputs into digital signals. this converter can control six channels (ani0 to ani5) of analog inputs. a/d conversion can only be started by software. one of analog inputs ani0 to ani5 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time a/d conversion is complete. 10.2 8-bit a/d converter configuration the 8-bit a/d converter includes the following hardware. table 10-1. configuration of 8-bit a/d converter item configuration analog inputs 6 channels (ani0 to ani5) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0)
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 184 figure 10-1. block diagram of 8-bit a/d converter sample & hold circuit voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus av ss p-ch av dd ani4/p64 ani5/p65 ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads02 ads01 ads00 (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 holds the result of a/d conversion. each time a/d conversion ends, the conversion result in the successive approximation register is loaded into adcr0, which is an 8-bit register. adcr0 can be read with an 8-bit memory manipulation instruction. reset input makes adcr0 undefined. (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 185 (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. (5) series resistor string the series resistor string is configured between av dd and av ss . it generates the reference voltages with which analog inputs are compared. (6) ani0 to ani5 pins ani0 to ani5 are the 6-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply pins ani0 to ani5 with voltages that fall outside the rated range. if a voltage greater than av dd or less than av ss (even if within the absolute maximum rating) is applied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ss pin the av ss pin is a ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d converter is not being used. (8) av dd pin the av dd pin is an analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd pin, even while the a/d converter is not being used.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 186 10.3 8-bit a/d converter control registers the 8-bit a/d converter is controlled by the following two registers. ? a/d converter mode register 0 (adm0) ? analog input channel specification register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h. figure 10-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/f x 120/f x 96/f x 72/f x 60/f x 48/f x fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) m m m fr00 0 1 0 0 1 0 other than above conversion disabled conversion enabled setting prohibited m adcs0 0 fr02 fr01 fr00 0 0 0 adm0 <7> 6 5 4 symbol address after reset r/w ff80h 00h r/w 3210 notes 1. the specifications of fr02, fr01, and fr00 must be such that the a/d conversion time is at least 14 m s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 m s. cautions 1. bits 0 to 2 and 6 must be set to 0. 2. the result of conversion performed immediately after setting adcs0 is undefined. 3. the conversion result may be undefined after clearing adcs0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 187 (2) analog input channel specification register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets ads0 to 00h. figure 10-3. format of analog input channel specification register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification other than above ads02 0 0 0 0 1 1 ani0 ani1 ani2 ani3 ani4 ani5 setting prohibited ads01 0 0 1 1 0 0 ads00 0 1 0 1 0 1 caution bits 3 to 7 must be set to 0.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 188 10.4 8-bit a/d converter operation 10.4.1 basic operation of 8-bit a/d converter <1> select a channel for a/d conversion, using analog input channel specification register 0 (ads0). <2> the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av dd . <5> the series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av dd , the msb of sar is left set. if it is lower than half of av dd , the msb is reset. <6> bit 6 of sar is set automatically, and comparison shifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: bit 7 = 1: three quarters of av dd bit 7 = 0: one quarter of av dd the tap voltage is compared with the analog input voltage. bit 6 is set or reset according to the result of comparison. analog input voltage 3 tap voltage: bit 6 = 1 analog input voltage < tap voltage: bit 6 = 0 <7> comparison is repeated until bit 0 of sar is reached. <8> when comparison is completed for all of the 8 bits, a significant digital result is left in sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. the first a/d conversion value immediately after a/d conversion has been started may be undefined. 2. in standby mode, a/d converter operation is stopped.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 189 figure 10-4. basic operation of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 80h c0h or 40h a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or analog input channel specification register 0 (ads0) during a/d conversion, the ongoing a/d conversion is canceled. in this case, a/d conversion is restarted from the beginning, if adcs0 is set (1). reset input makes a/d conversion result register 0 (adcr0) undefined. 10.4.2 input voltage and conversion result the relationships between the analog input voltage at the analog input pins (ani0 to ani5) and the a/d conversion result (a/d conversion result register 0 (adcr0)) are represented by: adcr0 = int ( 256 + 0.5) or (adcr0 - 0.5) v in < (adcr0 + 0.5) int( ): function that returns the integer part of a parenthesized value v in : analog input voltage av dd : supply voltage for the a/d converter adcr0: value in a/d conversion result register 0 (adcr0) figure 10-5 shows the relationship between the analog input voltage and the a/d conversion result. v in av dd av dd 256 av dd 256
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 190 figure 10-5. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 191 10.4.3 operation mode of 8-bit a/d converter the a/d converter is initially in select mode. in this mode, analog input channel specification register 0 (ads0) is used to select an analog input channel from ani0 to ani5 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 1 triggers a/d conversion for a voltage applied to the analog input pin specified in analog input channel specification register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where adcs0 is 1 is written to adm0 again during a/d conversion, the ongoing session of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conversion, a/d conversion is stopped immediately. figure 10-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 5 2. m = 0 to 5
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 192 10.5 cautions related to 8-bit a/d converter (1) current consumption in standby mode in standby mode, the a/d converter stops operation. stopping conversion (bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0) can reduce the current consumption. figure 10-7 shows how to reduce the current consumption in standby mode. figure 10-7. how to reduce current consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for pins ani0 to ani5 be sure to keep the input voltage at ani0 to ani5 within the rating. if a voltage not lower than av dd or not higher than av ss (even within the absolute maximum rating) is input into a conversion channel, the conversion output of the channel becomes undefined, which may affect the conversion output of the other channels. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcr0) at the end of conversion and reading from adcr0 using instruction reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conversion and writing to a/d converter mode register 0 (adm0) or analog input channel specification register 0 (ads0) writing to adm0 or ads0 takes precedence. adcr0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediately after start of a/d conversion the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0) and drop the first conversion result.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 193 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the completion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operation is completed. figures 10-8 and 10-9 show the timing at which the conversion result is read. figure 10-8. conversion result read timing (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcr0 intad0 adcs0 figure 10-9. conversion result read timing (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcr0 intad0 adcs0
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 194 (6) noise prevention to maintain a resolution of 8 bits, watch for noise to the av dd and ani0 to ani5 pins. the higher the output impedance of the analog input source, the larger the effect by noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 10-10. figure 10-10. analog input pin treatment c = 100 to 1,000 pf if noise not lower than av dd or not higher than av ss is likely to come to the av dd pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd (7) ani0 to ani5 the analog input pins (ani0 to ani5) are alternate-function pins. they are also used as port pins (p60 to p65). if any of ani0 to ani5 has been selected for a/d conversion, do not execute input instructions for the ports; otherwise the conversion resolution may be reduced. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur that prevents an a/d conversion result from being obtained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed during a/d conversion, therefore, the a/d conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to adm0 occurs. in this case, adif0 may already be set if it is read-accessed immediately after adm0 is write-accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is restarted, adif0 must be cleared beforehand.
chapter 10 8-bit a/d converter ( m m m m pd789426 and 789446 subseries) users manual u15075ej1v0um00 195 figure 10-11. a/d conversion end interrupt request generation timing rewriting to adm0 (to begin conversion for anin) rewriting to adm0 (to begin conversion for anim) a/d conversion anin anin anim anim adif0 has been set, but conversion for anim has not been completed. adcr0 anin anin anim anim intad0 remarks 1. n = 0 to 5 2. m = 0 to 5 (9) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani5 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as the v dd pin, as shown in figure 10-12. figure 10-12. av dd pin handling main power source backup capacitor v dd av dd v ss av ss (10) av dd pin input impedance a series resistor string of several ten of k w is connected between the av dd and av ss pins. consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a parallel connection with the series resistor string, creating a large reference voltage differential.
users manual u15075ej1v0um00 196 [memo]
users manual u15075ej1v0um00 197 chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) 11.1 10-bit a/d converter functions the 10-bit a/d converter is a 10-bit resolution converter used to convert analog inputs into digital signals. this converter can control six channels (ani0 to ani5) of analog inputs. a/d conversion can only be started by software. one of analog inputs ani0 to ani5 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time a/d conversion is complete. 11.2 10-bit a/d converter configuration the 10-bit a/d converter includes the following hardware. table 11-1. configuration of 10-bit a/d converter item configuration analog inputs 6 channels (ani0 to ani5) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0)
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 198 figure 11-1. block diagram of 10-bit a/d converter sample & hold circuit voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus av ss p-ch av dd ani4/p64 ani5/p65 ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads02 ads01 ads00 (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 holds the result of a/d conversion. each time a/d conversion ends, the conversion result in the successive approximation register is loaded into adcr0, which is a 10-bit register. adcr0 can be read with a 16-bit memory manipulation instruction. reset input makes adcr0 undefined. symbol adcr0h (ff14h) 0 0 0 0 0 0 adcr0l (ff14h) ff14h, ff15h address after reset 0000h r/w r caution when the m m m m pd78f9436, a flash memory version of the m m m m pd789425 or m m m m pd789426, is used, this register can be accessed in 8-bit units. however, only an object file assembled with the m m m m pd789425 or m m m m pd789426 can be used. the same is also true for the m m m m pd78f9456, a flash memory version of the m m m m pd789445 or m m m m pd789446: this register can be accessed in 8-bit units, but only an object file assembled with the m m m m pd789445 or m m m m pd789446 can be used.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 199 (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. (5) series resistor string the series resistor string is configured between av dd and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani5 pins ani0 to ani5 are the 6-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply pins ani0 to ani5 with voltages that fall outside the rated range. if a voltage greater than av dd or less than av ss (even if within the absolute maximum rating) is applied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ss pin the av ss pin is a ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d converter is not being used. (8) av dd pin the av dd pin is an analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd pin, even while the a/d converter is not being used.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 200 11.3 10-bit a/d converter control registers the 10-bit a/d converter is controlled by the following two registers. ? a/d converter mode register 0 (adm0) ? analog input channel specification register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h. figure 11-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/f x 120/f x 96/f x 72/f x 60/f x 48/f x fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) m m m fr00 0 1 0 0 1 0 other than above conversion disabled conversion enabled setting prohibited m adcs0 0 fr02 fr01 fr00 0 0 0 adm0 <7> 6 5 4 symbol address after reset r/w ff80h 00h r/w 3210 notes 1. the specifications of fr02, fr01, and fr00 must be such that the a/d conversion time is at least 14 m s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 m s. cautions 1. bits 0 to 2 and 6 must be set to 0. 2. the result of conversion performed immediately after setting adcs0 is undefined. 3. the conversion result may be undefined after clearing adcs0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 201 (2) analog input channel specification register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 11-3. format of analog input channel specification register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification other than above ads02 0 0 0 0 1 1 ani0 ani1 ani2 ani3 ani4 ani5 setting prohibited ads01 0 0 1 1 0 0 ads00 0 1 0 1 0 1 caution bits 3 to 7 must be set to 0.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 202 11.4 10-bit a/d converter operation 11.4.1 basic operation of 10-bit a/d converter <1> select a channel for a/d conversion, using analog input channel specification register 0 (ads0). <2> the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av dd . <5> the series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av dd , the msb of sar is left set. if it is lower than half of av dd , the msb is reset. <6> bit 8 of sar is set automatically, and comparison shifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: bit 9 = 1: three quarters of av dd bit 9 = 0: one quarter of av dd the tap voltage is compared with the analog input voltage. bit 8 is set or reset according to the result of comparison. analog input voltage 3 tap voltage: bit 8 = 1 analog input voltage < tap voltage: bit 8 = 0 <7> comparison is repeated until bit 0 of sar is reached. <8> when comparison is completed for all of the 10 bits, a significant digital result is left in sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. the first a/d conversion value immediately after a/d conversion has been started may be undefined. 2. in standby mode, a/d converter operation is stopped.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 203 figure 11-4. basic operation of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or analog input channel specification register 0 (ads0) during a/d conversion, the ongoing a/d conversion is canceled. in this case, a/d conversion is restarted from the beginning, if adcs0 is set (1). reset input makes a/d conversion result register 0 (adcr0) undefined. 11.4.2 input voltage and conversion result the relationships between the analog input voltage at the analog input pins (ani0 to ani5) and the a/d conversion result (a/d conversion result register 0 (adcr0)) are represented by: adcr0 = int ( 1,024 + 0.5) or (adcr0 - 0.5) v in < (adcr0 + 0.5) int( ): function that returns the integer part of a parenthesized value v in : analog input voltage av dd : supply voltage for the a/d converter adcr0: value in a/d conversion result register 0 (adcr0) figure 11-5 shows the relationship between the analog input voltage and the a/d conversion result. v in av dd av dd 1,024 av dd 1,024
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 204 figure 11-5. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av dd
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 205 11.4.3 operation mode of 10-bit a/d converter the a/d converter is initially in select mode. in this mode, analog input channel specification register 0 (ads0) is used to select an analog input channel from ani0 to ani5 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 1 triggers a/d conversion for a voltage applied to the analog input pin specified in a/d input selection register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where adcs0 is 1 is written to adm0 again during a/d conversion, the ongoing session of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conversion, a/d conversion is stopped immediately. figure 11-6. software-started a/d conversion rewriting adm0 adcs0 = 1 overwriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 5 2. m = 0 to 5
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 206 11.5 cautions related to 10-bit a/d converter (1) current consumption in standby mode in standby mode, the a/d converter stops operation. stopping conversion (bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0) can reduce the current consumption. figure 11-7 shows how to reduce the current consumption in standby mode. figure 11-7. how to reduce current consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for pins ani0 to ani5 be sure to keep the input voltage at ani0 to ani5 within the rating. if a voltage not lower than av dd or not higher than av ss (even within the absolute maximum rating) is input into a conversion channel, the conversion output of the channel becomes undefined, which may affect the conversion output of the other channels. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcr0) at the end of conversion and reading from adcr0 using instruction reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conversion and writing to a/d converter mode register 0 (adm0) or analog input channel specification register 0 (ads0) writing to adm0 or ads0 takes precedence. adcr0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediately after start of a/d conversion the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0) and drop the first conversion result.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 207 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the completion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operation is completed. figures 11-8 and 11-9 show the timing at which the conversion result is read. figure 11-8. conversion result read timing (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcr0 intad0 adcs0 figure 11-9. conversion result read timing (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcr0 intad0 adcs0
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 208 (6) noise prevention to maintain a resolution of 10 bits, watch for noise to the av dd and ani0 to ani5 pins. the higher the output impedance of the analog input source, the larger the effect by noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 11-10. figure 11-10. analog input pin treatment c = 100 to 1,000 pf if noise not lower than av dd or not higher than av ss is likely to come to the av dd pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd (7) ani0 to ani5 the analog input pins (ani0 to ani5) are alternate-function pins. they are also used as port pins (p60 to p65). if any of ani0 to ani5 has been selected for a/d conversion, do not execute input instructions for the ports; otherwise the conversion resolution may be reduced. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur that prevents an a/d conversion result from being obtained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed during a/d conversion, therefore, the a/d conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to adm0 occurs. in this case, adif0 may already be set if it is read-accessed immediately after adm0 is write-accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is restarted, adif0 must be cleared beforehand.
chapter 11 10-bit a/d converter ( m m m m pd789436 and 789456 subseries) users manual u15075ej1v0um00 209 figure 11-11. a/d conversion end interrupt request generation timing a/d conversion adcr0 intad0 rewriting to adm0 (to begin conversion for anin) rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. anin anin anim anim anin anin anim anim remarks 1. n = 0 to 5 2. m = 0 to 5 (9) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani5 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as the v dd pin, as shown in figure 11-12. figure 11-12. av dd pin handling main power supply backup capacitor v dd av dd v ss av ss (10) av dd pin input impedance a series resistor string of several ten of k w is connected between the av dd and av ss pins. consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a parallel connection with the series resistor string, creating a large reference voltage differential.
users manual u15075ej1v0um00 210 [memo]
users manual u15075ej1v0um00 211 chapter 12 serial interface 20 12.1 serial interface 20 functions serial interface 20 has the following three modes. operation stop mode asynchronous serial interface (uart) mode 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains an uart-dedicated baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud rates by dividing the frequency of the clock input to the asck20 pin. (3) 3-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmission and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchronous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bit data transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75xl, 78k, and 17k series devices. 12.2 serial interface 20 configuration serial interface 20 includes the following hardware. table 12-1. configuration of serial interface 20 item configuration registers transmission shift register 20 (txs20) reception shift register 20 (rxs20) reception buffer register 20 (rxb20) control registers serial operation mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20)
chapter 12 serial interface 20 users manual u15075ej1v0um00 212 internal bus reception buffer register 20 (rxb20) switching of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) reception shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmission shift register 20 (txs20) transmission shift clock selector csie20 dap20 data phase control reception shift clock si20/p25/ rxd20 so20/p24/ txd20 4 parity operation stop bit addition reception data counter parity operation stop bit addition transmission data counter sl20, cl20, ps200, ps201 reception enabled reception clock detection clock start bit detection csie20 csck20 sck20/p23/ asck20 ss20/p22 clock phase control reception detected internal clock output external clock input transmission and reception clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus figure 12-1. block diagram of serial interface 20 note see figure 12-2 for the configuration of the baud rate generator. port mode register (pm24)
chapter 12 serial interface 20 users manual u15075ej1v0um00 213 reception detection clock transmission shift clock reception shift clock reception detected txe20 rxe20 csie20 selector selector selector 1/2 1/2 transmission clock counter reception clock counter 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 sck20/asck20/p23 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus figure 12-2. block diagram of baud rate generator 20
chapter 12 serial interface 20 users manual u15075ej1v0um00 214 (1) transmission shift register 20 (txs20) txs20 is a register in which transmission data is prepared. the transmission data is output from txs20 bit-serially. when the data length is seven bits, bits 0 to 6 of the data in txs20 will be transmission data. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory manipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and reception buffer register 20 (rxb20) are mapped at the same address, such that any attempt to read from txs20 results in a value being read from rxb20. (2) reception shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the reception data to reception buffer register 20 (rxb20). rxs20 cannot be manipulated directly by a program. (3) reception buffer register 20 (rxb20) rxb20 holds a reception data. a new reception data is transferred from reception shift register 20 (rxs20) every 1-byte data reception. when the data length is seven bits, the reception data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipulation instruction, but cannot be written. reset input makes rxb20 undefined. caution rxb20 and transmission shift register 20 (txs20) are mapped at the same address, such that any attempt to write to rxb20 results in a value being written to txs20. (4) transmission controller the transmission controller controls transmission. for example, it adds start, parity, and stop bits to the data in transmission shift register 20 (txs20), according to the setting of asynchronous serial interface mode register 20 (asim20). (5) reception controller the reception controller controls reception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during reception. if an error is detected, asynchronous serial interface status register 20 (asis20) is set according to the status of the error.
chapter 12 serial interface 20 users manual u15075ej1v0um00 215 12.3 serial interface 20 control registers serial interface 20 is controlled by the following registers. serial operation mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20) (1) serial operation mode register 20 (csim20) csim20 is used to make the settings related to 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. figure 12-3. format of serial operation mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20 outputs at the rising edge of sck20 ss20 pin selection function of ss20/p22 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is at high level in the idle state clock is high active, and sck20 is at low level in the idle state cautions 1. bits 4 and 5 must be set to 0. 2. csim20 must be cleared to 00h if uart mode is selected.
chapter 12 serial interface 20 users manual u15075ej1v0um00 216 (2) asynchronous serial interface mode register 20 (asim20) asim20 is used to make the settings related to asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. figure 12-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stop transmit operation enable rxe20 0 1 receive operation control receive operation stop receive operation enable ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must be set to 0. 2. if 3-wire serial i/o mode is selected, asim20 must be set to 00h. 3. switch operating modes after halting the serial transmit/receive operation.
chapter 12 serial interface 20 users manual u15075ej1v0um00 217 table 12-2. serial interface 20 operating mode settings (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 first bit shift clock p25/si20/ rxd20 pin function p24/so20/ txd20 pin function p23/sck20/ asck20 pin function 00 0 note 1 note 1 note 1 note 1 note 1 note 1 -- p25 p24 p23 other than above setting prohibited (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 first bit shift clock p25/si20/ rxd20 pin function p24/so20/ txd20 pin function p23/sck20/ asck20 pin function 01 external clock sck20 input 10 101 msb internal clock sck20 output 01 external clock sck20 input 00 11 1 note 2 note 2 01 01 lsb internal clock si20 note 2 so20 (cmos output) sck20 output other than above setting prohibited (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 first bit shift clock p25/si20/ rxd20 pin function p24/so20/ txd20 pin function p23/sck20/ asck20 pin function 1 external clock asck20 input 10 0 0 0 note 1 note 1 01 note 1 note 1 internal clock p22 txd20 (cmos output) p23 1 external clock asck20 input 01 0 0 0 1 note 1 note 1 note 1 note 1 internal clock p24 p23 1 external clock asck20 input 11 0 0 0 1 01 note 1 note 1 lsb internal clock rxd20 txd20 (cmos output) p23 other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p25 (cmos i/o). remark : dont care.
chapter 12 serial interface 20 users manual u15075ej1v0um00 218 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. asis20 is set with a 1-bit or 8-bit memory manipulation instruction. the contents of asis20 are undefined in 3-wire serial i/o mode. reset input sets asis20 to 00h. figure 12-5. format of asynchronous serial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543<2><1><0> no parity error has occurred. a parity error has occurred (when the parity of transmit data does not match). fe20 0 1 flaming error flag no framing error has occurred. a framing error has occurred (when stop bit is not detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (when the next receive operation is completed before the data is read from reception buffer register 20) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read reception buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error will occur.
chapter 12 serial interface 20 users manual u15075ej1v0um00 219 (4) baud rate generator control register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. figure 12-6. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 3-bit counter source clock selection tps203 tps202 tps201 tps200 0000 brgc20 symbol address after reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock input to the asck20 pin note setting prohibited (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) other than above tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 - note an external clock can be used only in uart mode. cautions 1. when writing to brgc00 during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc00 during a communication operation. 2. be sure not to select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 12 serial interface 20 users manual u15075ej1v0um00 220 the baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the asck20 pin. (a) generation of baud rate transmit/receive clock form system clock the transmit/receive clock is generated by scaling the system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency n: values in figure 12-6, determined by the values of tps200 to tps203 (2 n 8) table 12-3. example of relationships between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1 8
chapter 12 serial interface 20 users manual u15075ej1v0um00 221 (b) generation of baud rate transmit/receive clock from external clock input to asck20 pin the transmit/receive clock is generated by scaling the clock input from the asck20 pin. the baud rate of a clock generated from the clock input to the asck20 pin is estimated by using the following expression. [baud rate] = [hz] f asck : frequency of clock input to the asck20 pin table 12-4. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 12 serial interface 20 users manual u15075ej1v0um00 222 12.4 serial interface 20 operation serial interface 20 provides the following three modes. operation stop mode asynchronous serial interface (uart) mode 3-wire serial i/o mode 12.4.1 operation stop mode in operation stop mode, serial transfer is not executed, thereby reducing the power consumption. the p23/sck20/asck20, p24/so20/txd20, and p25/si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode operation disabled operation enabled csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 <7> 6 5 4 symbol address after reset r/w ff72h 00h r/w 3210 caution bits 4 and 5 must be set to 0.
chapter 12 serial interface 20 users manual u15075ej1v0um00 223 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 receive operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 caution bits 0 and 1 must be set to 0.
chapter 12 serial interface 20 users manual u15075ej1v0um00 224 12.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. this device incorporates uart-dedicated baud rate generator that enables communications at the desired baud rate. in addition, the baud rate can also be defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the midi standard. (1) register setting uart mode is set by serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), asynchronous serial interface status register 20 (asis20), and baud rate generator control register 20 (brgc20).
chapter 12 serial interface 20 users manual u15075ej1v0um00 225 (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. set csim20 to 00h when uart mode is selected. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20 outputs at the rising edge of sck20 ss20 pin selection function of ss20/p22 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is high level in the idle state clock is high active, and sck20 is low level in the idle state caution bits 4 and 5 must be set to 0.
chapter 12 serial interface 20 users manual u15075ej1v0um00 226 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must be set to 0. 2. switch operating modes after halting the serial transmit/receive operation.
chapter 12 serial interface 20 users manual u15075ej1v0um00 227 (c) asynchronous serial interface status register 20 (asis20) asis20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asis20 to 00h. pe20 0 1 parity error flag no parity error has occured a parity error has occured (when the parity of transmit data does not match) no framing error has occured a framing error has occured (when stop bit is not detected) note 1 no overrun error has occured an overrun error has occured note 2 (when the next receive operation is completed before data is read from reception buffer register 20) fe20 0 1 0 1 framing error flag overrun error flag ove20 0 0 0 0 0 pe20 fe20 ove20 asis20 76 54 symbol address after reset r/w ff71h 00h r 3 <2> <1> <0> notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read reception buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error will occur.
chapter 12 serial interface 20 users manual u15075ej1v0um00 228 (d) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 - setting prohibited 3-bit counter source clock selection external clock input to asck20 pin note other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 note can only be used in the uart mode. cautions 1. when writing to brgc20 during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 12 serial interface 20 users manual u15075ej1v0um00 229 the baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the asck20 pin. (i) generation of baud rate transmit/receive clock from system clock the transmit/receive clock is generated by scaling the system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency n: values in the above table determined by the settings of tps200 to tps203 (2 n 8) table 12-5. example of relationships between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1 8
chapter 12 serial interface 20 users manual u15075ej1v0um00 230 (ii) generation of baud rate transmit/receive clock from external clock input to asck20 pin the transmit/receive clock is generated by scaling the clock input from the asck20 pin. the baud rate of a clock generated from the clock input to the asck20 pin is estimated by using the following expression. [baud rate] = [hz] f asck : frequency of clock input to asck20 pin table 12-6. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 12 serial interface 20 users manual u15075ej1v0um00 231 (2) communication operation (a) data format the transmit/receive data format is as shown in figure 12-7. one data frame consists of a start bit, character bits, parity bit, and stop bit(s). the specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (asim20). figure 12-7. format of asynchronous serial interface transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame start bits .................. 1 bit character bits ........... 7 bits/8 bits parity bits.................. even parity/odd parity/0 parity/no parity stop bits.................... 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always ?0?. the serial transfer rate is selected by asim20 and baud rate generator control register 20 (brgc20). if a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (asis20).
chapter 12 serial interface 20 users manual u15075ej1v0um00 232 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a one-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity at transmission the parity bit is determined so that the number of bits with a value of 1 in the transmit data including the parity bit may be even. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data: 1 the number of bits with a value of 1 is an even number in transmit data: 0 at reception the number of bits with a value of 1 in the receive data including parity bit is counted, and if the number is odd, a parity error occurs. (ii) odd parity at transmission conversely to the even parity, the parity bit is determined so that the number of bits with a value of 1 in the transmit data including parity bit may be odd. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data: 0 the number of bits with a value of 1 is an even number in transmit data: 1 at reception the number of bits with a value of 1 in the receive data including parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to 0 irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error does not occur, irrespective of whether the parity bit is set to 0 or 1. (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error does not occur.
chapter 12 serial interface 20 users manual u15075ej1v0um00 233 (c) transmission a transmit operation is started by writing transmit data to transmission shift register 20 (txs20). the start bit, parity bit, and stop bit(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interrupt (intst20) is generated. figure 12-8. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite asynchronous serial interface mode register 20 (asim20) during a transmit operation. if the asim20 register is rewritten during transmission, subsequent transmission may not be able to be performed (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20.
chapter 12 serial interface 20 users manual u15075ej1v0um00 234 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set (1), a receive operation is enabled and sampling of the rxd20 pin input is performed. rxd20 pin input sampling is performed using the serial clock specified by asim20. when the rxd20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to reception buffer register 20 (rxb20), and a reception completion interrupt (intsr20) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr20 is not generated. figure 12-9. asynchronous serial interface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read reception buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
chapter 12 serial interface 20 users manual u15075ej1v0um00 235 (e) receive errors the following three errors may occur during a receive operation: a parity error, framing error, and overrun error. after data reception, an error flag is set in asynchronous serial interface status register 20 (asis20). receive error causes are shown in table 12-7. it is possible to determine what kind of error occurred during reception by reading the contents of asis20 in the reception error interrupt servicing (see figures 12-9 and 12-10 ). the contents of asis20 are reset (0) by reading reception buffer register 20 (rxb20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 12-7. receive error causes receive errors cause parity error transmission-time parity and reception data parity do not match framing error stop bit not detected overrun error reception of next data is completed before data is read from reception buffer register figure 12-10. receive error timing (a) parity error occurrence stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error occurrence stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 register are reset (0) by reading reception buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read reception buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
chapter 12 serial interface 20 users manual u15075ej1v0um00 236 (3) cautions related to uart mode (a) when bit 7 (txe20) of asynchronous serial interface mode register 20 (asim20) is cleared during transmission, be sure to set transmission shift register 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is cleared during reception, reception buffer register 20 (rxb20) and the receive completion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at a time indicated by <1> , rxb20 holds the previous data and intsr20 is not generated. when rxe20 is set to 0 at a time indicated by <2> , rxb20 renews the data and intsr20 is not generated. when rxe20 is set to 0 at a time indicated by <3> , rxb20 renews the data and intsr20 is generated.
chapter 12 serial interface 20 users manual u15075ej1v0um00 237 12.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. communication is performed using three lines: a serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed using serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), and baud rate generator control register 20 (brgc20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20 outputs at the rising edge of sck20 ss20 pin selection function of ss20/p22 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is at high level in the idle state clock is high active, and sck20 is at low level in the idle state caution bits 4 and 5 must be set to 0.
chapter 12 serial interface 20 users manual u15075ej1v0um00 238 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. when 3-wire serial i/o mode is selected, asim20 must be set to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error occurs). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 transmit data character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must be set to 0. 2. switch operating modes after halting the serial transmit/receive operation.
chapter 12 serial interface 20 users manual u15075ej1v0um00 239 (c) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 tps202 0 0 0 0 1 1 1 1 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 tps200 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 setting prohibited 3-bit counter source clock selection other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 cautions 1. when writing to brgc20 during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. if the internal clock is used as the serial clock for 3-wire serial i/o mode, set bits tps200 to tps203 to set the frequency of the serial clock. to obtain the frequency to be set, use the following expression. when an external clock is used, setting brgc20 is not necessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n: values in the above table determined by the settings of tps200 to tps203 (1 n 8) f x 2 n + 1
chapter 12 serial interface 20 users manual u15075ej1v0um00 240 (2) communication operation in 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in synchronization with the serial clock. transmission shift register (txs20/sio20) and reception shift register (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). then transmit data is held in the so20 latch and output from the so20 pin. also, receive data input to the si20 pin is latched in the reception buffer register (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/sio20 and rxs20 stops automatically, and the interrupt request signal (intcsi20) is generated. figure 12-11. 3-wire serial i/o mode timing (1/7) (i) master operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output.
chapter 12 serial interface 20 users manual u15075ej1v0um00 241 figure 12-11. 3-wire serial i/o mode timing (2/7) (ii) slave operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (iii) slave operation (when dap20 = 0, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 note 1 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state.
chapter 12 serial interface 20 users manual u15075ej1v0um00 242 figure 12-11. 3-wire serial i/o mode timing (3/7) (iv) master operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20 (v) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20.
chapter 12 serial interface 20 users manual u15075ej1v0um00 243 figure 12-11. 3-wire serial i/o mode timing (4/7) (vi) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state. (vii) master operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20
chapter 12 serial interface 20 users manual u15075ej1v0um00 244 figure 12-11. 3-wire serial i/o mode timing (5/7) (viii) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. (ix) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state.
chapter 12 serial interface 20 users manual u15075ej1v0um00 245 figure 12-11. 3-wire serial i/o mode timing (6/7) (x) master operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 do7 note do6 do5 do4 do3 do2 do1 di7 di6 di5 di4 di3 di2 di1 sck20 so20 si20 sio20 write intcsi20 di0 do0 note the value of the last bit previously output is output. (xi) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 sck20 si20 so20 sio20 write intcsi20 do7 note do6 do5 do4 do3 do2 do1 do0 di0 note the value of the last bit previously output is output.
chapter 12 serial interface 20 users manual u15075ej1v0um00 246 figure 12-11. 3-wire serial i/o mode timing (7/7) (xii) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 note 1 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state. (3) transfer start serial transfer is started by setting transfer data to the transmission shift register (txs20/sio20) when the following two conditions are satisfied. bit 7 (csie20) of serial operation mode register 20 (csim20) = 1 internal serial clock is stopped or sck20 is high after 8-bit serial transfer. caution if csie20 is set to 1 after data is written to txs20/sio20, transfer does not start. termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (intcsi20).
users manual u15075ej1v0um00 247 chapter 13 lcd controller/driver 13.1 lcd controller/driver functions the functions of the lcd controller/driver of the m pd789426, 789436, 789446, and 789456 subseries are as follows. (1) automatic output of segment and common signals based on automatic display data memory read (2) two different display modes: ? 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) operation with a subsystem clock table 13-1 lists the maximum number of pixels that can be displayed in each display mode. table 13-1. number of segment outputs and maximum number of pixels bias method time slots common signals used maximum number of segments maximum number of pixels 3 com0 to com2 15 (5 segments 3 commons) m pd789426, 789436 subseries 4 com0 to com3 5 20 (5 segments 4 commons) 3 com0 to com2 45 (15 segments 3 commons) m pd789446, 789456 subseries 1/3 4 com0 to com3 15 60 (15 segments 4 commons) 13.2 lcd controller/driver configuration the lcd controller/driver includes the following hardware. table 13-2. configuration of lcd controller/driver item configuration display outputs segment signals: 5 ( m pd789426 and 789436 subseries) 15 ( m pd789446 and 789456 subseries) common signals: 4 (com0 to com3) control registers lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) lcd voltage amplification control register 0 (lcdva0)
chapter 13 lcd controller/driver 248 users manual u15075ej1v0um00 figure 13-1. block diagram of lcd controller/driver internal bus lcdc03 lcdc02 lcdc01 lcdc00 2 2 prescaler lcd clock selector selector lcdcl f clk 2 6 f clk 2 7 f clk 2 8 f clk 2 9 lcd clock control register 0 (lcdc0) lcdon0 vaon0 lips0 lcdm02 lcdm01 lcdm00 lcd display mode register 0 (lcdm0) lcd drive voltage controller v lc2 v lc1 v lc0 segment driver common driver com0 com1 com2 com3 3 3210 3210 65 74 fa00h display data memory lcdon0 selector segment driver 3210 3210 65 74 fa04h (fa0eh) note lcdon0 s4 (s14) timing controller f x /2 5 f x /2 6 f x /2 7 f xt s0 voltage amplifier gain lcd voltage amplification control register 0 (lcdva0) note the parenthesized values apply to the pd789446 and 789456 subseries. f lcd selector m
chapter 13 lcd controller/driver users manual u15075ej1v0um00 249 13.3 registers controlling lcd controller/driver ? lcd display mode register 0 (lcdm0) ? lcd clock control register 0 (lcdc0) ? lcd voltage amplification control register 0 (lcdva0) (1) lcd display mode register 0 (lcdm0) lcdm0 specifies whether to enable display operation. it also specifies the operation mode, lcd drive power supply, and display mode. lcdm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdm0 to 00h.
chapter 13 lcd controller/driver 250 users manual u15075ej1v0um00 figure 13-2. format of lcd display mode register 0 lcdon0 vaon0 0 lips0 0 0 0 lcdm00 lcdm0 symbol address after reset r/w ffb0h 00h r/w <7><6>5<4>3210 lcd controller/driver display mode selection lcdm00 0 1 4 3 lcd display enable/disable lcdon0 0 1 display off display on segment pin/common pin output control bit note lips0 0 1 lcd controller/driver operation mode note vaon0 0 1 no internal voltage amplification (normal operation) internal voltage amplification enabled (low-voltage operation) output ground level to segment/common pin output deselect level to segment pin and lcd waveform to common pin number of time slices bias mode 1/3 1/3 note when the lcd display panel is not used, the vaon0 and lips0 must be set to 0 to reduce power consumption. cautions 1. bits 1 to 3 and 5 must be set to 0. 2. when operating vaon0, follow the procedure described below. a. to stop voltage amplification after switching display status from on to off: 1) set to display off status by setting lcdon0 = 0. 2) disable outputs of all the segment buffers and common buffers by setting lips0 = 0. 3) stop voltage amplification by setting vaon0= 0. b. to stop voltage amplification during display on status: setting prohibited. be sure to stop voltage amplification after setting display off. c. to set display on from voltage amplification stop status: 1) start voltage amplification by setting vaon0 = 1, then wait for about 500 ms. 2) set all the segment buffers and common buffers to non-display output status by setting lips0 = 1. 3) set display on by setting lcdon0 = 1.
chapter 13 lcd controller/driver users manual u15075ej1v0um00 251 (2) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd clock and frame frequency. lcdc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdc0 to 00h. figure 13-3. format of lcd clock control register 0 lcdc03 lcdc02 lcdc01 lcdc00 lcdc0 symbol address after reset r/w ffb2h 00h r/w 76543210 internal clock (f lcd ) selection note lcdc03 0 0 1 1 lcdc02 0 1 0 1 lcd clock (lcdcl) selection lcdc01 0 0 1 1 lcdc00 0 1 0 1 0000 f lcd /2 6 f lcd /2 7 f lcd /2 8 f lcd /2 9 f xt (32.768 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) note specify an internal clock (f lcd ) frequency of at least 32 khz. cautions 1. bits 4 to 7 must be set to 0. 2. before changing the lcdc0 setting, be sure to stop voltage amplification (vaon0 = 0). 3. set the frame frequency to 128 hz or lower. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. table 13-3 lists the frame frequencies used when f xt (32.768 khz) is supplied to the internal clock (f clk1 ). table 13-3. frame frequencies (hz) lcd clock (f lcd ) display duty ratio f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) 1/3 21 43 85 171 note 1/4 16 32 64 128 note this setting is prohibited because it causes the frame frequency to exceed 128 hz.
chapter 13 lcd controller/driver 252 users manual u15075ej1v0um00 (3) lcd voltage amplification control register 0 (lcdva0) lcdva0 controls the voltage amplification level during the voltage amplifier operation. figure 13-4. format of lcd voltage amplification control register 0 0 gain lcdva0 symbol address after reset r/w ffb3h 00h r/w 7654321<0> gain 0 1 1.5 times (specification of the lcd panel used is 4.5 v.) 1.0 times (specification of the lcd panel used is 3 v.) 0 0 0 0 00 reference voltage (v lc2 ) level selection note note select the settings according to the specifications of the lcd panel that is used. caution before changing the lcdva0 setting, be sure to stop voltage amplification (vaon0 = 0). remark the typ. value is indicated as the reference voltage (v lc2 ) value.
chapter 13 lcd controller/driver users manual u15075ej1v0um00 253 13.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. <1> set the frame frequency using lcd clock control register 0 (lcdc0). <2> set the voltage amplification level using lcd voltage amplification control register 0 (lcdva0). gain = 0: v lc0 = 4.5 v, v lc1 = 3 v, v lc2 = 1. 5 v gain = 1: v lc0 = 3 v, v lc1 = 2 v, v lc2 = 1 v <3> set the time division using lcdm00 (bit 0 of lcd display mode register 0 (lcdm0)). <4> enable voltage amplification by setting vaon0 (bit 6 of lcdm0) (vaon0 = 1). <5> wait for 500 ms or more after setting vaon0. <6> set lips0 (bit 4 of lcdm0) (lips0 = 1) and output the deselect potential. <7> start output corresponding to each data memory by setting lcdon0 (bit 7 of lcdm0) (lcdon0 =1). 13.5 lcd display data memory the lcd display data memory is mapped at addresses fa00h to fa0eh. data in the lcd display data memory can be displayed on the lcd panel using the lcd controller/driver. figure 13-5 shows the relationship between the contents of the lcd display data memory and the segment/common outputs. that part of the display data memory which is not used for display can be used as ordinary ram. figure 13-5. relationship between lcd display data memory contents and segment/common outputs ( m m m m pd789446, 789456 subseries) s14 fa0eh s13 fa0dh s12 fa0ch s11 s2 fa02h s1 fa01h s0 fa00h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution no memory has been installed as the higher 4 bits of the lcd display data memory. be sure to set 0 to them.
chapter 13 lcd controller/driver 254 users manual u15075ej1v0um00 13.6 common and segment signals each pixel of the lcd panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (lcd drive voltage, v lcd ). it turns off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segment signals for an lcd panel would deteriorate it. to avoid this problem, this lcd panel is driven with ac voltage. (1) common signals each common signal is selected sequentially according to a specified number of time slots at the timing listed in table 13-4. in the static display mode, the same signal is output to com0 to com3 in common. in the three-time slot mode, keep the com3 pin open. table 13-4. com signals com signal number of time slots com0 com1 com2 com3 three-time slot mode open four-time slot mode (2) segment signals the segment signals correspond to lcd display data memory. bits 0, 1, 2, and 3 of each byte are read in synchronization with com0, com1, com2, and com3, respectively. if the contents of each bit are 1, it is converted to the select voltage, and if 0, it is converted to the deselect voltage. the conversion results are output to the segment pins. check, with the information given above, what combination of the front-surface electrodes (corresponding to the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. bit 3 of the lcd display data memory is not used for lcd display in the three-time slot mode. so this bit can be used for purposes other than display. lcd display data memory bits 4 to 7 are fixed to 0. (3) output waveforms of common and segment signals voltages listed in table 13-5 are output as common and segment signals. when both common and segment signals are at the select voltage, a display-on voltage of v lcd is obtained. the other combinations of the signals correspond to the display-off voltage. table 13-5. lcd drive voltage segment signal select signal level deselect signal level common signal v ss0 /v lc0 v lc1 /v lc2 select signal level v lc0 /v ss0 Cv lcd /+v lcd C v lcd /+ v lcd deselect signal level v lc2 /v lc1 C v lcd /+ v lcd C v lcd /+ v lcd 1 3 1 3 1 3 1 3 1 3 1 3
chapter 13 lcd controller/driver users manual u15075ej1v0um00 255 figure 13-6 shows the common signal waveforms, and figure 13-7 shows the voltages and phases of the common and segment signals. figure 13-6. common signal waveforms comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc1 v lc2 t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency figure 13-7. voltages and phases of common and segment signals select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period
chapter 13 lcd controller/driver 256 users manual u15075ej1v0um00 13.7 display modes 13.7.1 three-time slot display example figure 13-9 shows how the 5-digit lcd panel having the display pattern shown in figure 13-8 is connected to the segment signals (s0 to s14) and the common signals (com0 to com2) of the m pd789446 or m pd789456 subseries chip. this example displays data 123.45 in the lcd panel. the contents of the display data memory (addresses fa00h to fa0eh) correspond to this display. the following description focuses on numeral 3. ( .) displayed in the third digit. to display 3. in the lcd panel, it is necessary to apply the select or deselect voltage to the s6 to s8 pins according to table 13-6 at the timing of the common signals com0 to com2. table 13-6. select and deselect voltages (com0 to com2) segment common s6 s7 s8 com0 select select deselect com1 select select deselect com2 select select - according to table 13-6, it is determined that the display data memory location (fa06h) that corresponds to s6 must contain x111. figure 13-10 shows examples of lcd drive waveforms between the s6 signal and each common signal. when the select voltage is applied to s6 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd /Cv lcd , is generated to turn on the corresponding lcd segment. figure 13-8. three-time slot lcd display pattern and electrode connections s 3n+2 s 3n com0 com2 s 3n+1 com1 remark n = 0 to 4
chapter 13 lcd controller/driver users manual u15075ej1v0um00 257 figure 13-9. example of connecting three-time slot lcd panel 001011011101110 001110011011011 00 10 11 00 10 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 com 3 com 2 com 1 com 0 open x x x x x x: can be used to store any data because there is no corresponding segment in the lcd panel. : can always be used to store any data because of the three-time slot mode being used.
chapter 13 lcd controller/driver 258 users manual u15075ej1v0um00 figure 13-10. three-time slot lcd drive waveform examples v lc0 v lc2 com0 +v lcd 0 com0-s6 - v lcd v lc1 +1/3v lcd - 1/3v lcd v ss0 v lc0 v lc2 com1 v lc1 v ss0 v lc0 v lc2 com2 v lc1 v ss0 v lc0 v lc2 s6 v lc1 v ss0 +v lcd 0 com1-s6 - v lcd +1/3v lcd - 1/3v lcd +v lcd 0 com2-s6 - v lcd +1/3v lcd - 1/3v lcd t f
chapter 13 lcd controller/driver users manual u15075ej1v0um00 259 13.7.2 four-time slot display example figure 13-12 shows how the 7-digit lcd panel having the display pattern shown in figure 13-11 is connected to the segment signals (s0 to s14) and the common signals (com0 to com3) of the m pd789446 or m pd789456 subseries chip. this example displays data 123456.7 in the lcd panel. the contents of the display data memory (addresses fa00h to fa0eh) correspond to this display. the following description focuses on numeral 6. ( ) displayed in the seventh digit. to display 6. in the lcd panel, it is necessary to apply the select or deselect voltage to the s2 and s3 pins according to table 13-7 at the timing of the common signals com0 to com3. table 13-7. select and deselect voltages (com0 to com3) segment common s2 s3 com0 select select com1 deselect select com2 select select com3 select select according to table 13-7, it is determined that the display data memory location (fa02h) that corresponds to s2 must contain 1101. figure 13-13 shows examples of lcd drive waveforms between the s2 signal and the com0 or com1 signal (the waveforms for com2 and com3 have been left out from the drawing). when the select voltage is applied to s2 at the timing of com0, an alternate rectangle waveform, +v lcd /Cv lcd , is generated to turn on the corresponding lcd segment. figure 13-11. four-time slot lcd display pattern and electrode connections remark n = 0 to 7 com0 s 2n com1 s 2n+1 com2 com3
chapter 13 lcd controller/driver 260 users manual u15075ej1v0um00 figure 13-12. example of connecting four-time slot lcd panel 00010110111101 01111111101001 01100101011101 00101000101100 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 com 3 com 2 com 1 com 0
chapter 13 lcd controller/driver users manual u15075ej1v0um00 261 figure 13-13. four-time slot lcd drive waveform examples t f v lc0 v lc2 com0 +v lcd 0 com0-s2 - v lcd v lc1 +1/3v lcd - 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-s2 - v lcd +1/3v lcd - 1/3v lcd v lc0 v lc2 s2 v lc1 v ss
262 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 263 chapter 14 interrupt functions 14.1 interrupt function types the following two types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupt this interrupt undergoes mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 14-1. a standby release signal is generated. 5 external and 9 internal interrupt sources are incorporated as maskable interrupts. 14.2 interrupt sources and configuration a total of 15 non-maskable and maskable interrupts are incorporated as interrupt sources (see table 14-1 ).
chapter 14 interrupt functions 264 users manual u15075ej1v0um00 table 14-1. interrupt source list interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable - intwdt watchdog timer overflow (with watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (with interval timer mode selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4intp3 pin input edge detection external 000ch (c) intsr20 end of serial interface 20 uart reception 5 intcsi20 end of serial interface 20 3-wire sio transfer reception 000eh 6 intst20 end of serial interface 20 uart transmission 0012h 7 intwti interval timer interrupt 0014h 8 inttm90 generation of match signal of 16-bit timer 90 0016h 9 inttm50 generation of match signal of 8-bit timer 50 0018h 10 inttm60 generation of match signal of 8-bit timer 60 001ah 11 intad0 end of a/d conversion signal 001ch 12 intwt watch timer interrupt internal 001eh (b) maskable 13 intkr00 key return signal detection external 0020h (c) notes 1. priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and 13 is the lowest order. 2. basic configuration types (a) to (c) correspond to (a) to (c) in figure 14-1. remark there are two interrupt sources for the watchdog timer (intwdt): non-maskable and maskable interrupts (internal). either one (but not both) should be selected for actual use.
chapter 14 interrupt functions users manual u15075ej1v0um00 265 figure 14-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus intm0, intm1, krm00 interrupt request edge detector vector table address generator standby release signal intm0: external interrupt mode register 0 intm1: external interrupt mode register 1 krm00: key return mode register 00 if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 14 interrupt functions 266 users manual u15075ej1v0um00 14.3 registers controlling interrupt function the following five types of registers are used to control the interrupt functions. interrupt request flag registers 0, 1 (if0 and if1) interrupt mask flag registers 0, 1 (mk0 and mk1) external interrupt mode registers 0, 1 (intm0 and intm1) program status word (psw) key return mode register 00 (krm00) table 14-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 14-2. flags corresponding to interrupt request signal name interrupt request signal name interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr20/intcsi20 intst20 intwti inttm90 inttm50 inttm60 intad0 intwt intkr00 wdtif pif0 pif1 pif2 pif3 srif20 stif20 wtiif tmif90 tmif50 tmif60 adif0 wtif krif00 wdtmk pmk0 pmk1 pmk2 pmk3 srmk20 stmk20 wtimk tmmk90 tmmk50 tmmk60 admk0 wtmk krmk00
chapter 14 interrupt functions users manual u15075ej1v0um00 267 (1) interrupt request flag registers 0, 1 (if0 and if1) the interrupt request flag is set (1) when the corresponding interrupt request is generated or an instruction is executed. it is cleared (0) when an instruction is executed upon acknowledgement of an interrupt request or upon reset input. if0 and if1 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets if0 and if1 to 00h. figure 14-2. format of interrupt request flag registers 0 1 0 krif00 wtif adif0 tmif40 tmif30 tmif20 wtiif if1 ffe1h 00h r/w interrupt request flag no interrupt request signal is generated interrupt request signal is generated; interrupt request state xxifx <6> <5> <4> <3> <2> <1> 7 <0> stif20 0 srif20 pif3 pif2 pif1 pif0 wdtif if0 r/w ffe0h 00h r/w symbol address after reset 6 <5> <4> <3> <2> <1> <7> <0> cautions 1. bit 7 of if1 and bit 6 of if0 must be set to 0. 2. the wdtif flag is r/w enabled only when a watchdog timer is used as an interval timer. if the watchdog timer mode 1 or 2 is used, set the wdtif flag to 0. 3. because port 3 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode.
chapter 14 interrupt functions 268 users manual u15075ej1v0um00 (2) interrupt mask flag registers 0, 1 (mk0 and mk1) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. mk0 and mk1 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 14-3. format of interrupt mask flag registers 0 1 1 krmk00 wtmk admk0 tmmk40 tmmk30 tmmk20 wtimk mk1 ffe5h ffh r/w interrupt servicing control interrupt servicing enabled interrupt servicing disabled <6> <5> <4> <3> <2> <1> 7 <0> xxmk stmk20 1 srmk20 pmk3 pmk2 pmk1 pmk0 wdtmk mk0 r/w ffe4h ffh r/w symbol address after reset 6 <5> <4> <3> <2> <1> <7> <0> cautions 1. bits 7 of mk1 and bit 6 of mk0 must be set to 1. 2. if the wdtmk flag is read when the watchdog timer is used in watchdog timer mode 1 or 2, its value becomes undefined. 3. because port 3 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode.
chapter 14 interrupt functions users manual u15075ej1v0um00 269 (3) external interrupt mode register 0 (intm0) this register is used to specify a valid edge for intp0 to intp2. intm0 is set with an 8-bit memory manipulation instruction. reset input sets intm0 to 00h. figure 14-4. format of external interrupt mode register 0 0 0 1 1 es21 es20 es11 es10 es01 es00 0 0 intm0 r/w ffech 00h r/w 76543210 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 symbol address after reset intp0 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp1 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp2 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es00 es01 es11 es10 es20 es21 cautions 1. bits 0 and 1 must be set to 0. 2. before setting the intm0 register, be sure to set the relevant interrupt mask flag to 1 to disable interrupts. after that, clear (0) the interrupt request flag, then set the interrupt mask flag to 0 to enable interrupts.
chapter 14 interrupt functions 270 users manual u15075ej1v0um00 (4) external interrupt mode register 1 (intm1) intm1 is used to specify a valid edge for intp3. intm1 is set with an 8-bit memory manipulation instruction. reset input sets intm1 to 00h. figure 14-5. format of external interrupt mode register 1 000000 es31 es30 intm1 76543210 es31 0 0 1 1 intp3 valid edge selection es30 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffedh 00h r/w cautions 1. bits 2 to 7 must be set to 0. 2. before setting intm1, set pmk3 to 1 to disable interrupts. after that, clear (0) pif3, then set pmk3 to 0 to enable interrupts. (5) program status word (psw) the program status word is a register used to hold the instruction execution result and the current status for interrupt requests. the ie flag to set maskable interrupt enable/disable is mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei, di). when a vectored interrupt is acknowledged, the psw is automatically saved into a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 14-6. configuration of program status word ie z 0 ac 0 0 1 cy psw 76543210 ie 0 1 02h symbol after reset used when normal instruction is executed interrupt acknowledgement enabled/disabled disabled enabled
chapter 14 interrupt functions users manual u15075ej1v0um00 271 (6) key return mode register 00 (krm00) this register sets the pin that detects a key return signal (falling edge of port 0). krm00 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm00 to 00h. figure 14-7. format of key return mode register 00 0 1 0000000 krm000 krm00 fff5h 00h r/w address after reset r/w key return signal detection control no detection detection (detecting falling edge of port 0) 654321 70 krm000 symbol cautions 1. bits 1 to 7 must be set to 0. 2. before setting krm00, always set bit 6 of mk1 (krmk00 = 1) to disable interrupts. after setting krm00, clear krmk00 after clearing bit 6 of if1 (krif00 = 0) to enable interrupts. 3. when p00 to p03 are in input mode, on-chip pull-up resistors are connected to p00 to p03 by the setting of krm000. after switching to output mode, the on-chip pull-up resistors are cut off. however, key return signal detection continues. figure 14-8. block diagram of falling edge detector p00/kr0 p01/kr1 p02/kr2 p03/kr3 falling edge detector krmk00 krif00 set signal standby release signal key return mode register 00 (krm00) note selector note selector that selects the pin used for falling edge input
chapter 14 interrupt functions 272 users manual u15075ej1v0um00 14.4 interrupt servicing operation 14.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector table are loaded to the pc, and then program execution branches. figure 14-9 shows the flow from non-maskable interrupt request generation to acknowledgement, figure 14-10 shows the timing of non-maskable interrupt acknowledgement, and figure 14-11 shows the acknowledgement operation when a number of non-maskable interrupts are generated. caution during non-maskable interrupt service program execution, do not input another non-maskable interrupt request; if it is input, the service program will be interrupted and the new non- maskable interrupt request will be acknowledged.
chapter 14 interrupt functions users manual u15075ej1v0um00 273 figure 14-9. flow from generation of non-maskable interrupt request to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing starts wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 14-10. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 14-11. non-maskable interrupt request acknowledgment second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 14 interrupt functions 274 users manual u15075ej1v0um00 14.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vectored interrupt is acknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in table 14-3. refer to figures 14-13 and 14-14 for the timing of interrupt request acknowledgement. table 14-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated immediately before bt or bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. a pending interrupt is acknowledged when the status where it can be acknowledged is set. figure 14-12 shows the algorithm of interrupt request acknowledgement. when a maskable interrupt request is acknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servicing, use the reti instruction. figure 14-12. interrupt request acknowledgment program algorithm start xxif = 1 ? xxmk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending xxif: interrupt request flag xxmk: interrupt mask flag ie: flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable) 1 f cpu
chapter 14 interrupt functions users manual u15075ej1v0um00 275 figure 14-13. interrupt request acknowledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt if the interrupt request has generated an interrupt request flag (xxif) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n - 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution. figure 14-13 shows an example using the 8-bit data transfer instruction mov a, r. because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of mov a, r. figure 14-14. interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execution) clock cpu nop mov a, r saving psw and pc, and jump to interrupt servicing interrupt servicing program interrupt 8 clocks if the interrupt request flag (xxif) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after execution of the next instruction is complete. figure 14-14 shows an example whereby an interrupt request was generated in the 2nd clock of nop (a 2-clock instruction). in this case, the interrupt request will be processed after execution of mov a, r, which follows nop, is complete. caution when interrupt request flag registers 0 and 1 (if0 and if1), or interrupt mask flag registers 0 and 1 (mk0 and mk1) are being accessed, interrupt requests will be held pending. 14.4.3 multiple interrupt servicing multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. if multiple interrupts are generated at the same time, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to table 14-1 ).
chapter 14 interrupt functions 276 users manual u15075ej1v0um00 figure 14-15. example of multiple interrupts example 1. acknowledging multiple interrupts intyy ei main servicing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is acknowledged during the servicing of interrupt intxx and multiple interrupts are performed. before each interrupt request is acknowledged, the ei instruction is issued and the interrupt request is enabled. example 2. multiple interrupts are not performed because interrupts are disabled intyy ei main servicing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupt requests are disabled (the ei instruction has not been issued) in the interrupt intxx servicing, the interrupt request intyy is not acknowledged and multiple interrupts are not performed. intyy is held pending and is acknowledged after intxx servicing is completed. ie = 0: interrupt requests disabled
chapter 14 interrupt functions users manual u15075ej1v0um00 277 14.4.4 putting interrupt requests on hold if an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. such instructions (interrupt request pending instructions) are as follows. instructions that manipulate interrupt request flag registers 0, 1 (if0 and if1) instructions that manipulate interrupt mask flag registers 0, 1 (mk0 and mk1)
278 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 279 chapter 15 standby function 15.1 standby function and configuration 15.1.1 standby function the standby function is to reduce the power consumption of the system and can be effected in the following two modes: (1) halt mode this mode is set when the halt instruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduce the power consumption as much as the stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is executed. the stop mode stops the main system clock oscillator and stops the entire system. the power consumption of the cpu can be substantially reduced in this mode. the data memory can be retained at the low voltage (v dd = 1.8 v). therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. the stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscillator stabilizes after the stop mode has been released. if processing must be resumed immediately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. in addition, the statuses of the output latch of the i/o ports and output buffer are also retained. caution to set the stop mode, be sure to stop the operations of the peripheral hardware, and then execute the stop instruction.
chapter 15 standby function 280 users manual u15075ej1v0um00 15.1.2 register controlling standby function the wait time after the stop mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 15 /f x , not 2 17 /f x , after reset input. figure 15-1. format of oscillation stabilization time select register osts2 0 0 1 00000 osts2 osts1 osts0 osts r/w fffah 04h r/w 76543210 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 setting prohibited symbol address after reset oscillation stabilization time selection other than above m caution the wait time after the stop mode is released does not include the time from stop mode release to clock oscillation start (?a? in the figure below), regardless of whether stop mode is released by reset input or by interrupt generation. v ss a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 15 standby function users manual u15075ej1v0um00 281 15.2 standby function operation 15.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. the operation status in the halt mode is shown in the following table. table 15-1. halt mode operating status halt mode operation status while the main system clock is running halt mode operation status while the subsystem clock is r unning item while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running main system clock oscillation enabled oscillation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of halt mode. 16-bit timer operation enabled operation stopped tm50 operation enabled note 1 8-bit timer tm60 operation enabled operation enabled note 2 watch timer operation enabled operation enabled note 3 operation enabled operation enabled note 4 watchdog timer operation enabled operation stopped serial interface operation enabled operation stopped note 5 a/d converter operation stopped lcd controller/driver operation enabled operation enabled note 3 operation enabled operation enabled note 4 external interrupt operation enabled note 6 notes 1. operation is enabled only when input signal from timer 60 (timer 60 operation is enabled) is selected as the count clock. 2. operation is enabled when tmi60 is selected as the count clock. 3. operation is enabled while the main system clock is selected. 4. operation is enabled while the subsystem clock is selected. 5. operation is enabled only when external clock is selected. 6. maskable interrupt that is not masked
chapter 15 standby function 282 users manual u15075ej1v0um00 (2) releasing halt mode the halt mode can be released by the following three types of sources: (a) releasing by unmasked interrupt request the halt mode is released by an unmasked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed. if the interrupt is disabled, the instruction at the next address is executed. figure 15-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation remarks 1. the broken line indicates the case where the interrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt processing is performed: 9 to 10 clocks when vectored interrupt processing is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request the halt mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.
chapter 15 standby function users manual u15075ej1v0um00 283 (c) releasing by reset input when the halt mode is released by the reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. figure 15-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x : 6.55 ms) reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark f x : main system clock oscillation frequency table 15-2. operation after releasing halt mode releasing source mkxx ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 x retains halt mode non-maskable interrupt request - x executes interrupt servicing reset input - - - - reset processing x: dont care
chapter 15 standby function 284 users manual u15075ej1v0um00 15.2.2 stop mode (1) setting and operation status of stop mode the stop mode is set by executing the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been executed, the wait time set by the oscillation stabilization time select register (osts) elapses, and then an operation mode is set. the operation status in the stop mode is shown in the following table. table 15-3. stop mode operating status stop mode operation status while the main system clock is running item while the subsystem clock is r unning while the sub system clock is not r unning main system clock oscillation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of stop mode. 16-bit timer operation stopped tm50 operation enabled note 1 8-bit timer tm60 operation enabled note 2 watch timer operation enabled note 3 operation stopped watchdog timer operation enabled operation stopped serial interface operation enabled note 4 a/d converter operation stopped lcd controller/driver operation enabled note 3 operation stopped external interrupt operation enabled note 5 notes 1. operation is enabled only when input signal from timer 60 (timer 60 operation is enabled) is selected as the count clock. 2. operation is enabled when tmi60 is selected as the count clock. 3. operation is enabled while the subsystem clock is selected. 4. operation is enabled only when external clock is selected. 5. maskable interrupt that is not masked
chapter 15 standby function users manual u15075ej1v0um00 285 (2) releasing stop mode the stop mode can be released by the following two types of sources: (a) releasing by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed. if the interrupt is disabled, the instruction at the next address is executed. figure 15-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark the broken line indicates the case where the interrupt request that has released the standby mode is acknowledged.
chapter 15 standby function 286 users manual u15075ej1v0um00 (b) releasing by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 15-5. releasing stop mode by reset input stop instruction reset signal wait stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period remark f x : main system clock oscillation frequency table 15-4. operation after releasing stop mode releasing source mkxx ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 x retains stop mode reset input - - - - reset processing x: dont care
users manual u15075ej1v0um00 287 chapter 16 reset function the following two operations are available to generate reset signals. (1) external reset input by reset pin (2) internal reset by watchdog timer runaway time detection external and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 16-1. each pin has a high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. the reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (see figures 16-2 to 16-4 .) cautions 1. for an external reset, input a low level for 10 m m m m s or more to the reset pin. 2. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 16-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop
chapter 16 r eset f unction 288 users manual u15075ej1v0um00 figure 16-2. reset timing by reset input x1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 16-3. reset timing by overflow in watchdog timer x1 overflow in watchdog timer internal reset signal port pin hi-z during normal operation reset period (oscillation continues) normal operation (reset processing) oscillation stabilization time wait figure 16-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin delay delay hi-z stop instruction execution during normal operation reset period (oscillation stops) stop status (oscillation stops) normal operation (reset processing) oscillation stabilization time wait
chapter 16 r eset f unction users manual u15075ej1v0um00 289 table 16-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose register undefined note 2 port (p0 to p3, p5, p7) (output latch) 00h port (p8, p9) (output latch) note 3 00h port mode register (pm0 to pm3, pm5, pm7) ffh port mode register (pm8, pm9) note 3 ffh pull-up resistor option register (pu0, pub2, pub3, pub7) 00h pull-up resistor option register (pub8 note 3 , pub9 note 3 ) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time select register (osts) 04h timer counter (tm90) 0000h compare register (cr90) ffffh control register (tmc90) 00h 16-bit timer capture register (tcp90) undefined timer counter (tm50, tm60) 00h compare register (cr50, cr60, crh60) undefined 8-bit timer mode control register (tmc50, tmc60) 00h watch timer mode control register (wtm) 00h clock select register (wdcs) 00h watchdog timer mode register (wdtm) 00h serial operation mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface status register (asis20) 00h baud rate generator control register (brgc20) 00h transmit shift register (txs20) ffh serial interface receive buffer register (rxb20) undefined a/d conversion result register (adcr0) 0000h mode register (adm0) 00h a/d converter analog input channel specification register (ads0) 00h notes 1. during reset input and oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware remains unchanged after reset. 2. the post-reset values are retained in the standby mode. 3. m pd789426, 789436 subseries only
chapter 16 r eset f unction 290 users manual u15075ej1v0um00 table 16-1. hardware status after reset (2/2) hardware status after reset display mode register (lcdm0) 00h clock control register (lcdc0) 00h lcd controller/driver voltage amplification control register (lcdva0) 00h request flag register (if0, if1) 00h mask flag register (mk0, mk1) ffh external interrupt mode register (intm0, intm1) 00h interrupt key return mode register (krm00) 00h
users manual u15075ej1v0um00 291 chapter 17 m m m m pd78f9436, 78f9456 the m pd78f9436 and 78f9456 are available as the flash memory versions of the m pd789426, 789436, 789446, and 789456 subseries. the m pd78f9436 is a version with the internal rom of the m pd789426 and 789436 subseries replaced with flash memory and the m pd78f9456 is a version with the internal rom of the m pd789446 and 789456 subseries replaced with flash memory. the differences between the m pd78f9436, 78f9456 and the mask rom versions are shown in table 17-1. table 17-1. differences between m m m m pd78f9436, 78f9456 and mask rom versions flash memory version mask rom version part number item m pd78f9436 m pd78f9456 m pd789425, 789435 m pd789426, 789436 m pd789445, 789455 m pd789446, 789456 rom 12 kb 16 kb 12 kb 16 kb 12 kb 16 kb high-speed ram 512 bytes internal memory lcd display ram 5 bytes 15 bytes 5 bytes 15 bytes ic pin not provided provided v pp pin provided not provided electrical specifications varies depending on flash memory or mask rom versions. caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version.
chapter 17 m m m m pd78f9436, 78f9456 292 users manual u15075ej1v0um00 17.1 flash memory programming the on-chip program memory in the m pd78f9436 and 78f9456 is a flash memory. the flash memory can be written with the m pd78f9436 and 78f9456 mounted on the target system (on-board). connect the dedicated flash writer (flashpro iii (part no. fl-pr3, pg-fp3)) to the host machine and target system to write the flash memory. remark fl-pr3 is made by naito densei machida mfg co., ltd. 17.1.1 selecting communication mode the flash memory is written by using flashpro iii and by means of serial communication. select a communication mode from those listed in table 17-2. to select a communication mode, the format shown in figure 17-1 is used. each communication mode is selected by the number of v pp pulses shown in table 17-2. table 17-2. communication mode communication mode pins used number of v pp pulses 3-wire serial i/o sck20/asck20/p23 so20/txd20/p24 si20/rxd20/p25 0 uart txd20/so20/p24 rxd20/si20/p25 8 caution be sure to select a communication mode depending on the number of v pp pulses shown in table 17-2. figure 17-1. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n
chapter 17 m m m m pd78f9436, 78f9456 users manual u15075ej1v0um00 293 17.1.2 function of flash memory programming by transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. table 17-3 shows the major functions of flash memory programming. table 17-3. functions of flash memory programming function description batch erase erases all contents of memory batch blank check checks erased state of entire memory data write write to flash memory based on write start address and number of data written (number of bytes) batch verify compares all contents of memory with input data 17.1.3 flashpro iii connection example how the flashpro iii is connected to the m pd78f9436 or 78f9456 differs depending on the communication mode (3-wire serial i/o or uart). figures 17-2 and 17-3 show the connection in the respective modes. figure 17-2. flashpro iii connection example in 3-wire serial i/o mode v pp n note v dd reset sck so si gnd v pp v dd , av dd reset sck20 clk x1 si20 so20 v ss , av ss flashpro iii pd78f9436, 78f9456 m note n = 1, 2
chapter 17 m m m m pd78f9436, 78f9456 294 users manual u15075ej1v0um00 figure 17-3. flashpro iii connection example in uart mode v pp n note v dd reset si so gnd v pp v dd , av dd reset clk x1 rxd20 txd20 v ss , av ss flashpro iii pd78f9436, 78f9456 m note n = 1, 2
chapter 17 m m m m pd78f9436, 78f9456 users manual u15075ej1v0um00 295 17.1.4 example of settings for flashpro iii (pg-fp3) make the following settings when writing to flash memory using flashpro iii (pg-fp3). <1> load the parameter file. <2> select the serial mode and serial clock using the type command. <3> an example of settings for the pg-fp3 is shown below. table 17-4. example of settings for pg-fp3 communication mode example of settings for pg-fp3 number of v pp pulses note 1 comm port sio-ch0 on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz 3-wire serial i/o sio clk 1.0 mhz 0 comm port uart-ch0 cpu clk on target board on target board 4.1943 mhz uart uart bps 9600 bps note 2 8 notes 1. the number of v pp pulses supplied from flashpro iii when serial communication is initialized. the pins to be used for communication are determined according to the number of these pulses. 2. select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. remark comm port: selection of serial port sio clk: selection of serial clock frequency cpu clk: selection of source of cpu clock to be input
296 users manual u15075ej1v0um00 [memo]
users manual u15075ej1v0um00 297 chapter 18 mask options table 18-1. selection of mask option for pins pin mask option p50 to p53 whether a pull-up resistor is to be incorporated can be specified in 1-bit units. for p50 to p53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. the mask option is selectable in 1-bit units. caution flash memory versions do not have a mask option-based on-chip pull-up resistor function.
users manual u15075ej1v0um00 298 [memo]
users manual u15075ej1v0um00 299 chapter 19 instruction set this chapter lists the instruction set of the m pd789426, 789436, 789446, and 789456 subseries. for the details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions users manual (u11047e) . 19.1 operation 19.1.1 operand identifiers and description methods operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. #: immediate data specification $: relative address specification !: absolute address specification [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either functional names (x, a, c, etc.) or absolute names (names in parenthesis in the table below, r0, r1, r2, etc.) can be used for description. table 19-1. operand identifiers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 3-4 special function register list for symbols of special function registers.
chapter 19 instruction set 300 users manual u15075ej1v0um00 19.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by address or register contents in parenthesis x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) v: exclusive logical sum (exclusive or) - : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 19.1.3 description of flag column (blank): unchanged 0: cleared to 0 1: set to 1 x: set/cleared according to the result r: previously saved value is restored
chapter 19 instruction set users manual u15075ej1v0um00 301 19.2 operation list mnemonic operands byte clock operation flag zaccy mov r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte x x x a, psw 2 4 a ? psw psw, a 2 4 psw ? axxx a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl+byte] 2 6 a ? (hl + byte) [hl+byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl+byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set 302 users manual u15075ej1v0um00 mnemonic operands byte clock operation flag zaccy movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 1 4 ax ? rp rp, ax note 14rp ? ax xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy ? a + byte x x x saddr, #byte 3 6 (saddr), cy ? (saddr) + byte x x x a, r 2 4 a, cy ? a + r x x x a, saddr 2 4 a, cy ? a + (saddr) x x x a, !addr16 3 8 a, cy ? a + (addr16) x x x a, [hl] 1 6 a, cy ? a + (hl) x x x a, [hl+byte] 2 6 a, cy ? a + (hl + byte) x x x addc a, #byte 2 4 a, cy ? a + byte + cy x x x saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy x x x a, r 2 4 a, cy ? a + r + cy x x x a, saddr 2 4 a, cy ? a + (saddr) + cy x x x a, !addr16 3 8 a, cy ? a + (addr16) + cy x x x a, [hl] 1 6 a, cy ? a + (hl) + cy x x x a, [hl+byte] 2 6 a, cy ? a + (hl + byte) + cy x x x sub a, #byte 2 4 a, cy ? a - byte x x x saddr, #byte 3 6 (saddr), cy ? (saddr) - byte x x x a, r 2 4 a, cy ? a - rxxx a, saddr 2 4 a, cy ? a - (saddr) x x x a, !addr16 3 8 a, cy ? a - (addr16) x x x a, [hl] 1 6 a, cy ? a - (hl) x x x a, [hl+byte] 2 6 a, cy ? a - (hl + byte) x x x note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set users manual u15075ej1v0um00 303 mnemonic operands byte clock operation flag zaccy subc a, #byte 2 4 a, cy ? a - byte - cy x x x saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy x x x a, r 2 4 a, cy ? a - r - cy x x x a, saddr 2 4 a, cy ? a - (saddr) - cy x x x a, !addr16 3 8 a, cy ? a - (addr16) - cy x x x a, [hl] 1 6 a, cy ? a - (hl) - cy x x x a, [hl+byte] 2 6 a, cy ? a - (hl + byte) - cy x x x and a, #byte 2 4 a ? a byte x saddr, #byte 3 6 (saddr) ? (saddr) byte x a, r 2 4 a ? a rx a, saddr 2 4 a ? a (saddr) x a, !addr16 3 8 a ? a (addr16) x a, [hl] 1 6 a ? a (hl) x a, [hl+byte] 2 6 a ? a (hl + byte) x or a, #byte 2 4 a ? a byte x saddr, #byte 3 6 (saddr) ? (saddr) byte x a, r 2 4 a ? a rx a, saddr 2 4 a ? a (saddr) x a, !addr16 3 8 a ? a (addr16) x a, [hl] 1 6 a ? a (hl) x a, [hl+byte] 2 6 a ? a (hl + byte) x xor a, #byte 2 4 a ? a v byte x saddr, #byte 3 6 (saddr) ? (saddr) v byte x a, r 2 4 a ? a v r x a, saddr 2 4 a ? a v (saddr) x a, !addr16 3 8 a ? a v (addr16) x a, [hl] 1 6 a ? a v (hl) x a, [hl+byte] 2 6 a ? a v (hl + byte) x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set 304 users manual u15075ej1v0um00 mnemonic operands byte clock operation flag zaccy cmp a, #byte 2 4 a - byte x x x saddr, #byte 3 6 (saddr) - byte x x x a, r 2 4 a - rxxx a, saddr 2 4 a - (saddr) x x x a, !addr16 3 8 a - (addr16) x x x a, [hl] 1 6 a - (hl) x x x a, [hl+byte] 2 6 a - (hl + byte) x x x addw ax, #word 3 6 ax, cy ? ax + word x x x subw ax, #word 3 6 ax, cy ? ax - word x x x cmpw ax, #word 3 6 ax - word x x x inc r 2 4 r ? r + 1 x x saddr 2 4 (saddr) ? (saddr) + 1 x x dec r 2 4 r ? r + 1 x x saddr 2 4 (saddr) ? (saddr) - 1xx incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1x rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1x rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1x rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1x set1 saddr.bit 3 6 (saddr.bit) ? 1 sfr.bit 3 6 sfr.bit ? 1 a.bit 2 4 a.bit ? 1 psw.bit 3 6 psw.bit ? 1xxx [hl].bit 2 10 (hl).bit ? 1 clr1 saddr.bit 3 6 (saddr.bit) ? 0 sfr.bit 3 6 sfr.bit ? 0 a.bit 2 4 a.bit ? 0 psw.bit 3 6 psw.bit ? 0xxx [hl].bit 2 10 (hl).bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set users manual u15075ej1v0um00 305 mnemonic operands byte clock operation flag zaccy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr push psw 1 2 (sp - 1) ? psw, sp ? sp - 1 rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x bc $saddr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw.bit = 1 bf saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw.bit = 0 dbnz b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set 306 users manual u15075ej1v0um00 19.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmovmov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a.
chapter 19 instruction set users manual u15075ej1v0um00 307 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 19 instruction set 308 users manual u15075ej1v0um00 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
users manual u15075ej1v0um00 309 appendix a development tools the following development tools are available for development of systems using the m pd789426, 789436, 789446, and 789456 subseries. figure a-1 shows development tools. support to pc98-nx series unless specified otherwise, the products supported by ibm pc/at? compatibles can be used in pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. windows unless specified otherwise, windows indicates the following operating systems. windows 3.1 windows 95 windows nt? ver.4.0
appendix a development tools 310 users manual u15075ej1v0um00 figure a-1. development tools language processing software assembler package c compiler package system simulator device file c compiler source file integrated debugger embedded software os host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion adapter target system flash programmer flash memory writing adapter flash memory flash memory writing tools power supply unit
appendix a development tools users manual u15075ej1v0um00 311 a.1 language processing software program that converts program written in mnemonic into object codes that can be executed by microcontroller. in addition, automatic functions to generate symbol table and optimize branch instructions are also provided. used in combination with optional device file (df789456). the assembler package is a dos-based application but may be used under the windows environment by using project manager of windows (included in the assembler package). ra78k0s assembler package part number: m s ra78k0s program that converts program written in c language into object codes that can be executed by microcontroller. used in combination with optional assembler package (ra78k0s) and device file (df789316). the c compiler package is a dos-based application but may be used under the windows environment by using project manager of windows (included in the assembler package). cc78k0s c compiler package part number: m s cc78k0s file containing the information inherent to the device. used in combination with optional ra78k0s, cc78k0s, and sm78k0s. df789456 note device file part number: m s df789456 source file of functions for generating object library included in c compiler package. necessary for changing object library included in c compiler package according to customers specifications. since this is a source file, its working environment does not depend on any particular operating system. cc78k0s-l c compiler source file part number: m s cc78k0s-l note df789456 is a common file that can be used with ra78k0s, cc78k0s, and sm78k0s. remark in the part number differs depending on the host machines and operating systems to be used. m s ra78k0s m s cc78k0s m s df789456 m s cc78k0s-l host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at compatibles english windows note 3.5" 2hc fd 3p16 hp9000 series 700 tm hp-ux tm (rel. 10.10) dat (dds) 3k13 3.5" 2hc fd 3k15 sparcstation tm sunos tm (rel. 4.1.1), solaris tm (rel. 2.5.1) 1/4" cgmt 3r13 news tm (risc) news-os tm (rel. 6.1) 3.5" 2hc fd note also operates under the dos environment.
appendix a development tools 312 users manual u15075ej1v0um00 a.2 flash memory writing tools flashpro iii (part no. fl-pr3, pg-fp3) flash programmer dedicated flash programmer for microcomputers incorporating flash memory fa-64gk flash memory writing adapter adapter for writing to flash memory and connected to flashpro iii. fa-64gk: for 64-pin plastic tqfp (fine pitch) (gk-9et type) remark the fl-pr3 and fa-64gk are products made by naito densei machida mfg. co., ltd. (tel +81-44- 822-3813).
appendix a development tools users manual u15075ej1v0um00 313 a.3 debugging tools a.3.1 hardware ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using 78k/0s series. supports integrated debugger (id78k0s-ns). used in combination with ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-70000-mc-ps-b ac adapter adapter for supplying power from ac 100 to 240 v outlet. ie-70000-98-if-c interface adapter adapter necessary when using pc-9800 series pc (except notebook type) as host machine of ie-78k0s-ns (c bus supported) ie-70000-cd-if-a pc card interface pc card and interface cable necessary when using notebook pc as host machine of ie-78k0s- ns (pcmcia socket supported) ie-70000-pc-if-c interface adapter interface adapter necessary when using ibm pc/at compatible as host machine of ie-78k0s- ns (isa bus supported) ie-70000-pci-if interface adapter adapter necessary when using personal computer incorporating pci bus as host machine of ie- 78k0s-ns ie-789456-ns-em1 emulation board board for emulating the peripheral hardware inherent to the device. used in combination with in- circuit emulator. np-64gk emulation probe probe to connect the in-circuit emulator and target system. used in combination with the tgk-064sbw and tgk-064sbp. tgk-064sbw, tgk-064sbp conversion adapter conversion socket to connect the np-64gk and a target system board on which a 64-pin plastic tqfp (fine pitch) (gk-9et type) can be mounted remarks 1. the np-64gk is a product made by naito densei machida mfg. co., ltd. (tel +81-44-822-3813). 2. the tgk-064sbw and tgk-064sbp are products made by tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools 314 users manual u15075ej1v0um00 a.3.2 software control program for debugging 78k/0s series. this program provides a graphical use interface. it runs on windows for personal computer users and on osf/motif tm for engineering work station users, and has visual designs and operationability that comply with these operating systems. in addition, it has a powerful debug function that supports c language. therefore, trace results can be displayed at a c language level by the window integration function that links source program, disassembled display, and memory display, to the trace result. this software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system. used in combination with optional device file (df789456). id78k0s-ns integrated debugger (supports in-circuit emulator ie-78k0s-ns) part number: m s id78k0s-ns remark in the part number differs depending on the host machines and operating systems to be used. m s id78k0s-ns host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at compatibles english windows note 3.5" 2hc fd note also operates under the dos environment. debugs program at c source level or assembler level while simulating operation of target system on host machine. sm78k0s runs under windows. by using sm78k0s, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. this enhances development efficiency and improves software quality. used in combination with optional device file (df789456). sm78k0s system simulator part number: m s sm78k0s file containing the information inherent to the device. used in combination with the optional ra78k0s, cc78k0s, and sm78k0s. df789456 note device file part number: m s df789456 note df789456 is a common file that can be used with ra78k0s, cc78k0s, and sm78k0s. remark in the part number differs depending on the host machines and operating systems to be used. m s sm78k0s host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at compatibles english windows note 3.5" 2hc fd note also operates under the dos environment.
users manual u15075ej1v0um00 315 appendix b embedded software the following embedded software is provided to perform the program development and maintenance of the m pd789426, 789436, 789446, and 789456 subseries effectively. subset os conformed to m itron. includes the nucleus of the mx78k0s. task control, event control, and time control are performed. in the task control, task execution sequences are controlled to switch the task to be executed next. the mx78k0s is a dos-based application. use this software in the dos prompt when running it on windows. mx78k0s os part number: m s mx78k0s remark in the part number differs depending on the host machines and operating systems to be used. m s mx78k0s host machine os supply media aa13 pc-9800 series japanese windows note 3.5" 2hd fd ab13 japanese windows note bb13 ibm pc/at compatibles english windows note 3.5" 2hc fd note also operates under the dos environment.
users manual u15075ej1v0um00 316 [memo]
users manual u15075ej1v0um00 317 appendix c register index c.1 register index (alphabetic order of register name) [a] analog input channel specification register 0 (ads0)........................................................................... ....... 187, 201 a/d conversion result register 0 (adcr0) ....................................................................................... ............ 184, 198 a/d converter mode register 0 (adm0)........................................................................................... ............. 186, 200 asynchronous serial interface mode register 20 (asim20).......................................................... 216, 223, 226, 238 asynchronous serial interface status register 20 (asis20)...................................................................... .... 218, 227 [b] baud rate generator control register 20 (brgc20) ............................................................................. 21 9, 228, 239 buzzer output control register 90 (bzc90) ...................................................................................... .................... 121 [c] carrier generator output control register 60 (tca60) ........................................................................... ............... 142 [e] 8-bit compare register 50 (cr50) ............................................................................................... ......................... 135 8-bit compare register 60 (cr60) ............................................................................................... ......................... 135 8-bit compare register h60 (crh60) ............................................................................................. ...................... 135 8-bit timer counter 50 (tm50) .................................................................................................. ............................ 136 8-bit timer counter 60 (tm60) .................................................................................................. ............................ 136 8-bit timer mode control register 50 (tmc50) ................................................................................... ........... 138, 139 8-bit timer mode control register 60 (tmc60) ................................................................................... ........... 140, 141 external interrupt mode register 0 (intm0) ..................................................................................... .................... 269 external interrupt mode register 1 (intm1) ..................................................................................... ............ 269, 270 [ i ] interrupt mask flag register 0, 1 (mk0, mk1) ................................................................................... .................... 268 interrupt request flag register 0, 1 (if0, if1) ................................................................................ ........................ 267 [k] key return mode register 00 (krm00) ............................................................................................ ..................... 271 [l] lcd clock control register 0 (lcdc0)........................................................................................... ....................... 251 lcd display mode register 0 (lcdm0) ............................................................................................ ............ 249, 250 lcd voltage amplification control register 0 (lcdva0) .......................................................................... ............. 252 [o] oscillation stabilization time select register (osts) .......................................................................... .................. 280 [p] port 0 (p0).................................................................................................................... .......................................... 81
appendix c register index 318 users manual u15075ej1v0um00 port 1 (p1).................................................................................................................... .......................................... 82 port 2 (p2).................................................................................................................... .......................................... 83 port 3 (p3).................................................................................................................... .......................................... 89 port 5 (p5).................................................................................................................... .......................................... 91 port 6 (p6).................................................................................................................... .......................................... 92 port 7 (p7).................................................................................................................... .......................................... 93 port 8 (p8).................................................................................................................... .......................................... 94 port 9 (p9).................................................................................................................... .......................................... 95 port mode register 0 (pm0)..................................................................................................... ......................... 96, 97 port mode register 1 (pm1)..................................................................................................... ......................... 96, 97 port mode register 2 (pm2)..................................................................................................... ................. 96, 97, 122 port mode register 3 (pm3)..................................................................................................... ................. 96, 97, 142 port mode register 5 (pm5)..................................................................................................... ......................... 96, 97 port mode register 7 (pm7)..................................................................................................... ......................... 96, 97 port mode register 8 (pm8)..................................................................................................... ......................... 96, 97 port mode register 9 (pm9)..................................................................................................... ......................... 96, 97 processor clock control register (pcc) ......................................................................................... ....................... 105 pull-up resistor option register 0 (pu0) ....................................................................................... ........................... 98 pull-up resistor option register b2 (pub2) ..................................................................................... ........................ 99 pull-up resistor option register b3 (pub3) ..................................................................................... ........................ 99 pull-up resistor option register b7 (pub7) ..................................................................................... ...................... 100 pull-up resistor option register b8 (pub8) ..................................................................................... ...................... 100 pull-up resistor option register b9 (pub9) ..................................................................................... ...................... 101 [r] receive buffer register 20 (rxb20) ............................................................................................. ........................ 214 [s] serial operation mode register 20 (csim20)................................................................................ 215, 222, 225, 237 subclock control register (css) ................................................................................................ ........................... 107 suboscillation mode register (sckm) ............................................................................................ ...................... 106 16-bit capture register 90 (tcp90)............................................................................................. .......................... 118 16-bit compare register 90 (cr90).............................................................................................. ......................... 118 16-bit timer counter 90 (tm90)................................................................................................. ............................ 118 16-bit timer mode control register 90 (tmc90) .................................................................................. .......... 119, 120 [t] transmit shift register 20 (txs20) ............................................................................................. .......................... 214 [w] watch timer mode control register (wtm) ........................................................................................ ................... 173 watchdog timer clock select register (wdcs) .................................................................................... ................. 179 watchdog timer mode register (wdtm) ............................................................................................ .................. 180
appendix c register index users manual u15075ej1v0um00 319 c.2 register index (alphabetic order of register symbol) [a] adcr0: a/d conversion result register 0......................................................................................... ......... 184, 198 adm0: a/d converter mode register 0 ............................................................................................. ....... 186, 200 ads0: analog input channel specification register 0............................................................................. . 187, 201 asim20: asynchronous serial interface mode register 20......................................................... 216, 223, 226, 23 8 asis20: asynchronous serial interface status register 20 ........................................................................ 218, 227 [b] brgc20: baud rate generator control register 20 .............................................................................. 219 , 228, 239 bzc90: buzzer output control register 90 ........................................................................................ ................ 121 [c] cr50: 8-bit compare register 50 ................................................................................................. ................... 135 cr60: 8-bit compare register 60 ................................................................................................. ................... 135 cr90: 16-bit compare register 90 ................................................................................................ .................. 118 crh60: 8-bit compare register h60 ............................................................................................... .................. 135 csim20: serial operation mode register 20............................................................................... 215, 222 , 225, 237 css: subclock control register.................................................................................................. ................... 107 [ i ] if0: interrupt request flag register 0.......................................................................................... ................. 267 if1: interrupt request flag register 1.......................................................................................... ................. 267 intm0: external interrupt mode register 0....................................................................................... ................ 269 intm1: external interrupt mode register 1....................................................................................... ........ 269, 270 [k] krm00: key return mode register 00 .............................................................................................. ................. 271 [l] lcdc0: lcd clock control register 0............................................................................................. ................... 251 lcdm0: lcd display mode register 0.............................................................................................. ......... 249, 280 lcdva0: lcd voltage amplification control register 0 ............................................................................ ........... 252 [m] mk0: interrupt mask flag register 0 ............................................................................................. ................. 268 mk1: interrupt mask flag register 1 ............................................................................................. ................. 268 [o] osts: oscillation stabilization time select register ............................................................................ ............ 280 [p] p0: port 0 ...................................................................................................................... .............................. 81 p1: port 1 ...................................................................................................................... .............................. 82 p2: port 2 ...................................................................................................................... .............................. 83 p3: port 3 ...................................................................................................................... .............................. 89
appendix c register index 320 users manual u15075ej1v0um00 p5: port 5...................................................................................................................... ............................... 91 p6: port 6...................................................................................................................... ............................... 92 p7: port 7...................................................................................................................... ............................... 93 p8: port 8...................................................................................................................... ............................... 94 p9: port 9...................................................................................................................... ............................... 95 pcc: processor clock control register ........................................................................................... ............... 105 pm0: port mode register 0....................................................................................................... ................. 96, 97 pm1: port mode register 1....................................................................................................... ................. 96, 97 pm2: port mode register 2....................................................................................................... ......... 96, 97, 122 pm3: port mode register 3....................................................................................................... ......... 96, 97, 142 pm5: port mode register 5....................................................................................................... ................. 96, 97 pm7: port mode register 7....................................................................................................... ................. 96, 97 pm8: port mode register 8....................................................................................................... ................. 96, 97 pm9: port mode register 9....................................................................................................... ................. 96, 97 pu0: pull-up resistor option register 0 ......................................................................................... .................. 98 pub2: pull-up resistor option register b2 ....................................................................................... .................. 99 pub3: pull-up resistor option register b3 ....................................................................................... .................. 99 pub7: pull-up resistor option register b7 ....................................................................................... ................ 100 pub8: pull-up resistor option register b8 ....................................................................................... ................ 100 pub9: pull-up resistor option register b9 ....................................................................................... ................ 101 [r] rxb20: receive buffer register 20 ............................................................................................... .................... 214 [s] sckm: suboscillation mode register .............................................................................................. ................. 106 [t] tca60: carrier generator output control register 60 ............................................................................. ........... 142 tcp90: 16-bit capture register 90 ............................................................................................... ..................... 118 tm50: 8-bit timer counter 50 .................................................................................................... ...................... 136 tm60: 8-bit timer counter 60 .................................................................................................... ...................... 136 tm90: 16-bit timer counter 90 ................................................................................................... ..................... 118 tmc50: 8-bit timer mode control register 50 ..................................................................................... ....... 138, 139 tmc60: 8-bit timer mode control register 60 ..................................................................................... ....... 140, 141 tmc90: 16-bit timer mode control register 90 .................................................................................... ...... 119, 120 txs20: transmit shift register 20............................................................................................... ...................... 214 [w] wdcs: watchdog timer clock select register ...................................................................................... ............ 179 wdtm: watchdog timer mode register .............................................................................................. .............. 180 wtm: watch timer mode control register .......................................................................................... ............ 173
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: 044-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 00.6 name company from: tel. fax facsimile message

▲Up To Search▲

Price & Availability of MPD789426GK-9ET

	To Download MPD789426GK-9ET Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .